Yasutaka Horiba - researchr alias

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Viewing Publication 1 - 8 from 8

2006

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC DesignTakayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba. ieicet, 89-C(11):1519-1525, 2006. [doi]

2005

A Method of Precise Estimation of Physical Parameters in LSI Interconnect StructuresToshiki Kanamoto, Tetsuya Watanabe, Mitsutoshi Shirota, Masayuki Terai, Tatsuya Kunikiyo, Kiyoshi Ishikawa, Yoshihide Ajioka, Yasutaka Horiba. ieicet, 88-A(12):3463-3470, 2005. [doi]

2001

A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace treeNiichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba. jssc, 36(2):249-257, 2001. [doi]

1999

The D30V/MPEG multimedia processorHidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba. micro, 19(4):38-47, 1999. [doi]

1991

A flexible multiport RAM compiler for data pathHirofumi Shinohara, Noriaki Matsumoto, Kumiko Fujimori, Yoshiki Tsujihashi, Hiroomi Nakao, Shuichi Kato, Yasutaka Horiba, Akiharu Tada. jssc, 26(3):343-349, March 1991. [doi]

1990

A 24-b 50-ns digital image signal processorShin-ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shuichi Kato, Masahiro Hatanaka, Hideo Ohira, Yoshiaki Kato, Mamoru Iwatsuki, Kinya Tabuchi, Yasutaka Horiba. jssc, 25(6):1484-1493, December 1990. [doi]

1988

A DSP line equalizer VLSI for TCM digital subscriber-line transmissionHideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba. jssc, 23(1):118-123, February 1988. [doi]

An SOI structure for flash A/D converterToshio Kumamoto, Masao Nakaya, Shigeru Kusunoki, Tadashi Nishimura, Nobuharu Yazawa, Yoichi Akasaka, Yasutaka Horiba. jssc, 23(1):198-201, February 1988. [doi]

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