Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko. An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. J. Solid-State Circuits, 31(6):773-783, 1996. [doi]
Abstract is missing.