Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko. An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. J. Solid-State Circuits, 31(6):773-783, 1996. [doi]
@article{MakinoNSMSM96,
title = {An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture},
author = {Hiroshi Makino and Yasunobu Nakase and Hiroaki Suzuki and Hiroyuki Morinaka and Hirofumi Shinohara and Koichiro Mashiko},
year = {1996},
doi = {10.1109/4.509863},
url = {https://doi.org/10.1109/4.509863},
researchr = {https://researchr.org/publication/MakinoNSMSM96},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {31},
number = {6},
pages = {773-783},
}