An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko. An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. J. Solid-State Circuits, 31(6):773-783, 1996. [doi]

Authors

Hiroshi Makino

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Yasunobu Nakase

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Hiroaki Suzuki

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Hiroyuki Morinaka

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Hirofumi Shinohara

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Koichiro Mashiko

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