Michio Yotsuyanagi - researchr alias

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Viewing Publication 1 - 7 from 7

2012

A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibrationYuji Nakajima, Norihito Kato, Akemi Sakaguchi, Toshio Ohkido, Kenji Shimomaki, Hiroko Masuda, Chikahiro Shiroma, Michio Yotsuyanagi, Takahiro Miki. cicc 2012: 1-4 [doi]

2010

A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating ArchitectureYuji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Norihito Kato, Tetsuya Matsumoto, Michio Yotsuyanagi. jssc, 45(4):707-718, 2010. [doi]

Low-Voltage Operational Active Inductor for LNA CircuitMasaaki Soda, Ningyi Wang, Michio Yotsuyanagi. ieicet, 93-A(12):2609-2615, 2010. [doi]

2000

A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displaysMuneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi. jssc, 35(11):1611-1618, 2000. [doi]

1999

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communicationsMuneo Fukaishi, Satoshi Nakamura, Akio Tajima, Yasushi Kinoshita, Yoshihiko Suemura, Hisamitsu Suzuki, Toshiro Itani, Hidenobu Miyamoto, Naoya Henmi, Tohru Yamazaki, Michio Yotsuyanagi. jssc, 34(9):1325-1330, 1999. [doi]

1998

A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architectureMuneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi. jssc, 33(12):2139-2147, 1998. [doi]

1995

A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D converterMichio Yotsuyanagi, Hiroshi Hasegawa, Motoi Yamaguchi, Masaki Ishida, Kazuya Sone. jssc, 30(12):1533-1537, December 1995. [doi]

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