Dustin Dunwell - researchr alias

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Viewing Publication 1 - 10 from 10

2019

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOSShayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto. isscc 2019: 482-484 [doi]

2017

All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital ConvertersShuai Chen, Luke Wang, Hong Zhang, Rosanah Murugesu, Dustin Dunwell, Anthony Chan Carusone. tvlsi, 25(9):2552-2560, 2017. [doi]

2014

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADCMike Bichan, Dustin Dunwell, Qiwei Wang, Anthony Chan Carusone. iscas 2014: 1320-1323 [doi]

2013

Channel characterization using jitter measurementsDustin Dunwell, Atul Gupta, Anthony Chan Carusone. iscas 2013: 2666-2669 [doi]

Modeling Oscillator Injection Locking Using the Phase Domain ResponseDustin Dunwell, Anthony Chan Carusone. tcas, 60-I(11):2823-2833, 2013. [doi]

2012

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-onDustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble. cicc 2012: 1-4 [doi]

2010

Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiverDustin Dunwell, Anthony Chan Carusone. cicc 2010: 1-4 [doi]

A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOSDustin Dunwell, Anthony Chan Carusone. iscas 2010: 205-208 [doi]

2007

Computer design of super-orthogonal space-time trellis codesMichael Bale, Brady Laska, Dustin Dunwell, Francois Chan, Hamid Jafarkhani. TWC, 6(2):463-467, 2007. [doi]

2006

24 GHz Low-Noise Amplifiers using High Q Series-Stub Transmission Lines in 0.18µm CMOSDustin Dunwell, Brian Frank. ccece 2006: 1918-1921 [doi]

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