Abstract is missing.
- Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memoryMichael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae-Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim. 1-4 [doi]
- Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistorKentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi. 1-4 [doi]
- Design of low-noise CMOS MEMS accelerometer with techniques for thermal stability and stable DC biasingSiew-Seong Tan, Cheng-Yen Liu, Li-Ken Yeh, Yi-Hsiang Chiu, Michael S.-C. Lu, Klaus Y. J. Hsu. 1-4 [doi]
- An inside body power and bidirectional data transfer IC module pairEdward K. F. Lee. 1-4 [doi]
- Millimeter-wave 14dBm CMOS power amplifier with input-output distributed transformersAndrea Pallotta, Wissam Eyssa, Luca Larcher, Riccardo Brama. 1-4 [doi]
- An energy-efficient ring-oscillator digital PLLJohn Crossley, Eric Naviasky, Elad Alon. 1-4 [doi]
- An integrated 33.5dBm linear 2.4GHz power amplifier in 65nm CMOS for WLAN applicationsAli Afsahi, Lawrence E. Larson. 1-4 [doi]
- A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-ampYoung-Ju Kim, Kyung-Hoon Lee, Seung-Hak Ji, Yi-Gi Kwon, Seung-Hoon Lee, Kyoung-Jun Moon, Michael Choi, Ho-Jin Park, Byeong-ha Park. 1-4 [doi]
- A 10 bit piecewise linear cascade interpolation dac with loop gain ratio controlSungwoo Lee, Kiduk Kim, Kyusung Park, Changbyung Park, Byunghun Lee, Jinyong Jeon, Seungchul Jung, Jin Huh, Junhyeok Yang, Hyunsik Kim, Gyu-Hyeong Cho. 1-4 [doi]
- 2 fully integrated GPS radio with cellular/WiFi Co-existencePaul Yu, Todd Sepke, Belal Helal, Shervin Shekarchian, Danilo Gerna, Konstantinos Sarrigeorgidis, Lydi Smaini, Arnab Mitra, James Li, Brian Brunn, Gregory Uehara, Thomas Cho. 1-4 [doi]
- A 25Gb/s laser diode driver with mutually coupled peaking inductors for optical interconnectsNorio Chujo, Tsuneo Kawamata, Kenichi Ohhata, Toshinobu Ohno. 1-4 [doi]
- D-band CMOS transmitter and receiver for multi-giga-bit/sec wireless data linkZhiwei Xu, Qun Jane Gu, Yi-Cheng Wu, Adrian Tang 0002, Yu-Ling Lin, Ho-Hsian Chen, Chewnpu Jou, Mau-Chung Frank Chang. 1-4 [doi]
- Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOSVivek Joshi, Michael Wieckowski, Gregory K. Chen, David Blaauw, Dennis Sylvester. 1-4 [doi]
- Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processorSeungjin Lee, Jinwook Oh, Minsu Kim, Junyoung Park, Joonsoo Kwon, Joo-Young Kim, Hoi-Jun Yoo. 1-4 [doi]
- A self oscillating class D audio amplifier with 0.0012% THD+N and 116.5 dB dynamic rangeJingxue Lu, Ranjit Gharpurey. 1-4 [doi]
- 192-channel CMOS neurochemical microarrayMeisam Honarvar Nazari, Hamed Mazhab-Jafari, Lian Leng, Axel Guenther, Roman Genov. 1-4 [doi]
- A 1.56GHz wide-tuning all digital FBAR-based PLL in 0.13µm CMOSJulie R. Hu, Richard C. Ruby, Brian P. Otis. 1-4 [doi]
- Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequencyKeith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De. 1-4 [doi]
- Dynamic NBTI management using a 45nm multi-degradation sensorPrashant Singh, Eric Karl, Dennis Sylvester, David Blaauw. 1-4 [doi]
- A low-supply PLL with Enhanced Cascode Compensation and a low-supply-sensitivity CCOXiong Liu, Alan N. Willson Jr.. 1-4 [doi]
- A 43.5mW 77GHz receiver front-end in 65nm CMOS suitable for FM-CW Automotive RadarRoc Berenguer, Gui Liu, Abe Akhiyat, Keya Kamtikar, Yang Xu. 1-4 [doi]
- Smart CMOS substrates for bioelectronic interfaces: Overview and trendsMarco Tartagni. 1-8 [doi]
- A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channelJun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong June Park. 1-4 [doi]
- Single event transient mitigation in cache memory using transient error checking circuitsXiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith E. Holbert. 1-4 [doi]
- Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiverDustin Dunwell, Anthony Chan Carusone. 1-4 [doi]
- Modelling and Measurements on minimum-width transmission-lines from 10-67GHz in 65nm CMOSPaul T. M. van Zeijl, Henry T. van der Zanden, Bob B. A. Theunissen, Henk A. H. Termeer. 1-4 [doi]
- Data-dependant sense-amplifier flip-flop for low power applicationsFarshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy. 1-4 [doi]
- Highly integrated and tunable RF front-ends for reconfigurable multi-band transceiversHooman Darabi. 1-8 [doi]
- 280-GHz schottky diode detector in 130-nm digital CMOSRuonan Han, Yaming Zhang, Dominique Coquillat, Julie Hoy, Hadley Videlier, Wojciech Knap, Elliott Brown, K. O. Kenneth. 1-4 [doi]
- A signal-agnostic compressed sensing acquisition system for wireless and implantable sensorsFred Chen, Anantha P. Chandrakasan, Vladimir Stojanovic. 1-4 [doi]
- Digital link pre-emphasis with dynamic driver impedance modulationRanko Sredojevic, Vladimir Stojanovic. 1-4 [doi]
- Technology variability from a design perspectiveBorivoje Nikolic, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Ji Hoon Park, Seng Oon Toh. 1-8 [doi]
- A 10 GHz low phase noise VCO employing current reuse and capacitive power combiningDiptendu Ghosh, Stewart S. Taylor, Yulin Tan, Ranjit Gharpurey. 1-4 [doi]
- Statistical modeling and post manufacturing configuration for scaled analog CMOSGokce Keskin, Jonathan Proesel, Larry T. Pileggi. 1-4 [doi]
- Parameter-specific ring oscillator for process monitoring at the 45 nm nodeLynn T.-N. Wang, Nuo Xu, Seng Oon Toh, Andrew R. Neureuther, Tsu-Jae King Liu, Borivoje Nikolic. 1-4 [doi]
- Fully integrated on-chip DC-DC converter with a 450x output rangeSudhir S. Kudva, Ramesh Harjani. 1-4 [doi]
- A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOSTakeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera. 1-4 [doi]
- Varactor-based signal restoration for near-speed-of-light surfing global interconnectSuwen Yang, Robert J. Drost, Mark R. Greenstreet, Shahriar Mirabbasi, Frank O'Mahony. 1-4 [doi]
- 2Bart De Vuyst, Pieter Rombouts. 1-4 [doi]
- A CMOS programmable gain amplifier with a novel DC-offset cancellation techniqueXiaojie Chu, Min Lin, Zheng Gong, Yin Shi, Fa Foster Dai. 1-4 [doi]
- A 77-GHz to 90-GHz bidirectional amplifier for half-duplex front-endsJoohwa Kim, Mehmet Parlak, James F. Buckwalter. 1-4 [doi]
- Ramp signal generation in Voltage mode CCM Random switching Frequency Buck converter for conductive EMI reductionEdward N. Y. Ho, Philip K. T. Mok. 1-4 [doi]
- A 70 GHz 10.2 mW self-demodulator for OOK modulation in 65-nm CMOS technologyXia Li, Peter G. M. Baltus, Paul T. M. van Zeijl, Dusan M. Milosevic, Arthur H. M. van Roermund. 1-4 [doi]
- A frequency-shift based CMOS magnetic biosensor with spatially uniform sensor transducer gainHua Wang, Constantine Sideris, Ali Hajimiri. 1-4 [doi]
- Reliability analysis of analog circuits using quadratic lifetime worst-case distance predictionXin Pan, Helmut Graeb. 1-4 [doi]
- A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correctionSarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Qadeer Khan, Pavan Kumar Hanumolu. 1-4 [doi]
- A semi-passive UHF RFID tag with on-chip temperature sensorWenyi Che, Dechao Meng, Xuegui Chang, Wei Chen, Lifang Wang, YuQing Yang, Conghui Xu, Xi Tan, Na Yan, Hao Min. 1-4 [doi]
- A programmable pulse UWB transmitter with 34% energy efficiency for multichannel neuro-recording systemsHenrique Miranda, Teresa H. Meng. 1-4 [doi]
- A novel readout IC with high noise immunity for charge-based touch screen panelsJunhyeok Yang, Seungchul Jung, Young-Jin Woo, Jinyong Jeon, Sungwoo Lee, Changbyung Park, Hyunsik Kim, Seung-Tak Ryu, Gyu-Hyeong Cho. 1-4 [doi]
- SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibrationPingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu. 1-4 [doi]
- 2 10b 204MS/s pipelined SAR ADC in 65nm CMOSYoung-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon. 1-4 [doi]
- Setup time, hold time and clock-to-Q delay computation under dynamic supply noiseTakaaki Okumura, Masanori Hashimoto. 1-4 [doi]
- A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/OsTaehyoun Oh, Ramesh Harjani. 1-4 [doi]
- Technology-circuit co-design of asymmetric SRAM cells for read stability improvementJae-Joon Kim, Rahul M. Rao, Keunwoo Kim. 1-4 [doi]
- A 27mW 2.2dB NF GPS receiver using a capacitive cross-coupled structure in 65nm CMOSHyunwon Moon, Seung-Chan Heo, Hwayeal Yu, Jinhyuck Yu, Ji-Soo Chang, Seung-Il Choi, Sangyoub Lee, Woo-Seung Choo, Byeong-ha Park. 1-4 [doi]
- A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOSJoseph F. Ryan 0002, Benton H. Calhoun. 1-4 [doi]
- A novel wideband 1-π model with accurate substrate modeling for on-chip spiral inductorsHuanhuan Zou, Jun Liu, Jincai Wen, Huang Wang, Lingling Sun, Zhiping Yu. 1-4 [doi]
- A 50-300-MHz low power and high linear active RF tracking filter for digital TV tuner ICsYang Sun, Chang-Jin Jeong, In-Young Lee, Jeong-Seon Lee, Sang-Gug Lee. 1-4 [doi]
- Digital phase tightening for millimeter-wave imagingKhoa M. Nguyen, Anthony Accardi, Helen Kim, Gregory W. Wornell, Charles Sodini. 1-4 [doi]
- A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3nsMark Jacunski, Darren Anand, Robert Busch, John Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale Pontius, Michael Roberge, Stephen Sliva. 1-4 [doi]
- Modeling of integrated RF passive devicesSharad Kapur, David E. Long. 1-8 [doi]
- A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receiversTina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune. 1-4 [doi]
- A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustmentTzu-Chien Hsueh, Sudhakar Pamarti. 1-4 [doi]
- A 2.4GHz mixed-signal polar power amplifier with low-power integrated filtering in 65nm CMOSDebopriyo Chowdhury, Lu Ye, Elad Alon, Ali M. Niknejad. 1-4 [doi]
- Loop finder analysis for analog circuitsG. Peter Fang, Rod Burt, Ning Dong. 1-4 [doi]
- A 77 GHz power amplifier using transformer-based power combiner in 90 nm CMOSTao-Yao Chang, Chao-Shiun Wang, Chorng-Kuang Wang. 1-4 [doi]
- A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOSKeita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda. 1-4 [doi]
- Specialty Foundry technology and design enablement for RF, high performance analog, and powerSamir Chaudhry, Marco Racanelli. 1-4 [doi]
- A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engineChih-Chi Cheng, Yi-Min Tsai, Liang-Gee Chen, Anantha P. Chandrakasan. 1-4 [doi]
- Dynamic push-pull operational amplifier for AMLCD common voltage driver using minimum current limiting circuitSeungchul Jung, Young-Jin Woo, Tae-Kyu Nam, Jinyong Jeon, Gyu-Ha Cho, Gyu-Hyeong Cho. 1-4 [doi]
- EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precisionNaoki Masunaga, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai. 1-4 [doi]
- Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bondingMitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka. 1-4 [doi]
- A 32nm 0.5V-supply dual-read 6T SRAMJente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka. 1-4 [doi]
- A dynamic timing control technique utilizing time borrowing and clock stretchingKwanyeob Chae, Saibal Mukhopadhyay, Chang-Ho Lee, Joy Laskar. 1-4 [doi]
- A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCsFred Chen, Anantha P. Chandrakasan, Vladimir Stojanovic. 1-4 [doi]
- A low power high reliability dual-path noise-cancelling LNA for WSN applicationsMing-Yeh Hsu, Chao-Shiun Wang, Chorng-Kuang Wang. 1-4 [doi]
- 1.5-GHz CMOS voltage-controlled oscillator based on thickness-field-excited piezoelectric AlN contour-mode MEMS resonatorsChengjie Zuo, Jan Van der Spiegel, Gianluca Piazza. 1-4 [doi]
- W-band pulsed radar receiver in low cost CMOSNing Zhang, K. O. Kenneth. 1-4 [doi]
- rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-ReceiverKazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho. 1-4 [doi]
- A 9µW 88dB DR fully-clocked switched-opamp ΔΣ modulator with novel power and area efficient resonatorJian Xu, Xiaobo Wu, Hanqing Wang, Bill Liu, Menglian Zhao. 1-4 [doi]
- 0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOSYasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai. 1-4 [doi]
- Spurious free time-to-digital conversion in an ADPLL using short dithering sequencesKhurram Waheed, Mahbuba Sheba, Robert Bogdan Staszewski, Fikret Dulger, Socrates D. Vamvakos. 1-4 [doi]
- 0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOSPo-Hung Chen, Koichi Ishida, Xin Zhang, Yasuaki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai. 1-4 [doi]
- Amorphous silicon 7 bit digital to analog converter on PENAritra Dey, Hongjiang Song, Tofayel Ahmed, Sameer M. Venugopal, David R. Allee. 1-4 [doi]
- Noise analysis of non-linear dynamic integrated circuitsAmir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs. 1-4 [doi]
- Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOSTao Jiang, Wing Liu, Freeman Y. Zhong, Charlie Zhong, Patrick Yin Chiang. 1-4 [doi]
- 100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applicationsMi-Jo Kim, Lee-Sup Kim. 1-4 [doi]
- Will CMOS amplifiers ever Kick-GaAs?Peter J. Zampardi. 1-4 [doi]
- Process variation tolerant all-digital multiphase DLL for DDR3 interfaceHeechai Kang, Kyungho Ryu, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung. 1-4 [doi]
- Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arraysBibiche M. Geuskens, Muhammad M. Khellah, Jaydeep Kulkarni, Tanay Karnik, Vivek De. 1-4 [doi]
- A novel equivalent circuit for on chip transmission lines modelingDajie Zeng, Hongrui Wang, Dongxu Yang, Li Zhang, Yan Wang, Zhiping Yu, Yaohui Zhang. 1-4 [doi]
- A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/HzFarhad Farhabakhshian, Thomas William Brown, Kartikeya Mayaram, Terri S. Fiez. 1-4 [doi]
- A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communicationsTsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda. 1-4 [doi]
- 82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correctionWenhuan Yu, Mehmet Aslan, Gabor C. Temes. 1-4 [doi]
- A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOSHsieh-Hung Hsieh, Fu-Lung Hsueh, Chewnpu Jou, Fred Kuo, Sean Chen, Tzu-Jin Yeh, Kevin Kai-Wen Tan, Po-yi Wu, Yu-Ling Lin, Ming-Hsien Tsai. 1-4 [doi]
- A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3Peiyuan Wan, Yun Chiu, Pingfen Lin. 1-4 [doi]
- V-band varactor-less interpolative-phase-tuning oscillators with multiphase outputsSujiang Rong, Howard C. Luong. 1-4 [doi]
- A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correctionSang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu. 1-4 [doi]
- Reconfigurable mobile stream processor for ray tracingHong-Yun Kim, Young-Jun Kim, Lee-Sup Kim. 1-4 [doi]
- A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOSTakashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura. 1-4 [doi]
- Equalizer design and performance trade-offs in ADC-based serial linksJaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe. 1-8 [doi]
- Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutionsGeert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal. 1-4 [doi]
- A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADCDavid T. Lin, Li Li, Shahin Farahani, Michael P. Flynn. 1-4 [doi]
- A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizerJeongseok Chae, Sanghyeon Lee, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes. 1-4 [doi]
- A 32-channel front-end for wireless HID using inverse-STF pre-filtering techniqueSherif Galal, Jurgen van Engelen, Jared Welz, Henrik Jensen, Khaled Abdelfattah, Felix Cheung, Sasi Kumar Arunachalam, Xicheng Jiang, Todd Brooks. 1-4 [doi]
- On the modeling of LDMOS RF power transistorsJohn Wood, Peter H. Aaen. 1-8 [doi]
- 7T SRAM enabling low-energy simultaneous block copyShunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto. 1-4 [doi]
- Event-driven data acquisition and continuous-time digital signal processingYannis P. Tsividis. 1-8 [doi]
- From pistons and gears to electronics and software: The coming transportation technology disruptionIan Wright. 1 [doi]
- Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFETShin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara. 1-4 [doi]
- A 10 GHz frequency-drift temperature compensated LC VCO with fast-settling low-noise voltage regulator in 0.13 µm CMOSHiroshi Akima, Aleksander Dec, Timothy Merkin, Kenji Suyama. 1-4 [doi]
- Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectorsAnthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao. 1-8 [doi]
- High-speed CMOS ring oscillators with low supply sensitivityXiaoyan Gui, Michael M. Green. 1-4 [doi]
- Improving SRAM Vmin and yield by using variation-aware BTI stressJiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun. 1-4 [doi]
- An offset phase-locked loop spread spectrum clock generator for SATA IIIChin-Yu Lin, Chun-Yu Chiang, Tai-Cheng Lee. 1-4 [doi]
- A customized design of DRAM controller for on-chip 3D DRAM stackingTao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin. 1-4 [doi]
- A 34.7-mW quad-core MIQP solver processor for robot controlHiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 1-4 [doi]
- 2 near-optimal MIMO detector in 0.18µm CMOSTae-Hwan Kim, In-Cheol Park. 1-4 [doi]
- A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technologyWei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu. 1-4 [doi]
- Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOSDavid E. Duarte, Suching Hsu, Keng L. Wong, Mingwei Huang, Greg Taylor. 1-4 [doi]
- A low-power multi-band ECoG/EEG interface ICFan Zhang, Apurva Mishra, Andrew G. Richardson, Stavros Zanos, Brian P. Otis. 1-4 [doi]
- A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitterGanesh K. Balachandran, Venkatesh Srinivasan, Vijay Rentala, Srinath Ramaswamy. 1-4 [doi]
- Simulation methodology and flow integration for 3D IC stress managementMark Nakamoto, Riko Radojcic, Wei Zhao, Vinay K. Dasarapu, Aditya P. Karmarkar, Xiaopeng Xu. 1-4 [doi]
- Smart universal control IC for high loaded factor resonant convertersYujia Yang, Fabio Bisogno, Sadachai Nittayarumphong, Matthias Radecker, Marc Fahlenkamp, Wolf-Joachim Fischer. 1-4 [doi]
- A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOSMaryam Fathi, David K. Su, Bruce A. Wooley. 1-4 [doi]
- A 4-port-inductor-based VCO coupling method for phase noise reductionZhiming Deng, Ali M. Niknejad. 1-4 [doi]
- A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip linesHae Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong June Park. 1-4 [doi]
- Layout-dependent proximity effects in deep nanoscale CMOSJohn Faricelli. 1-8 [doi]
- A low-noise analog baseband in 65nm CMOSHassan O. Elwan, Ahmet Tekin, Kenneth Pedrotti. 1-4 [doi]
- Modeling and simulation of transistor and circuit variability and reliabilityAsen Asenov, Binjie Cheng, Daryoosh Dideban, Urban Kovac, Negin Moezi, Campbell Millar, Gareth Roy, Andrew R. Brown, Scott Roy. 1-8 [doi]
- A 3-dimensional Vernier ring time-to-digital converter in 0.13µm CMOSJianjun Yu, Fa Foster Dai. 1-4 [doi]
- 3 sensor nodesYoonmyung Lee, Gregory K. Chen, Scott Hanson, Dennis Sylvester, David Blaauw. 1-8 [doi]
- A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOSWenjing Yin, Rajesh Inti, Pavan Kumar Hanumolu. 1-4 [doi]
- An energy-efficient SoC for closed-loop medical monitoring and interventionXiaoyu Zhang, Hanjun Jiang, Fule Li, Songyuan Cheng, Chun Zhang, Zhihua Wang. 1-4 [doi]
- A 140mA 90nm CMOS low drop-out regulator with -56dB power supply rejection at 10MHzAhmed Amer, Edgar Sánchez-Sinencio. 1-4 [doi]
- A 5-MHz 91% peak-power-efficiency buck regulator with auto-selectable peak- and valley-current controlMengmeng Du, Hoi Lee. 1-4 [doi]
- HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor systemDavid E. Duarte, Paola Zepeda, Suching Hsu, Atul Maheshwari, Greg Taylor. 1-4 [doi]
- A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidthBrian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu. 1-4 [doi]
- An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selectionJonathan Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi. 1-4 [doi]
- A micropower delta-sigma modulator based on a self-biased super inverter for neural recording systemsLe Wang, Luke Theogarajan. 1-4 [doi]
- A +5dBFS third-order extended dynamic range single-loop ΔΣ modulatorNima Maghari, Skyler Weaver, Un-Ku Moon. 1-4 [doi]
- A 40-Gb/s optical transceiver front-end in 45nm SOI CMOS technologyJoohwa Kim, James F. Buckwalter. 1-4 [doi]
- Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnectsShayak Banerjee, Kanak B. Agarwal, Michael Orshansky. 1-4 [doi]
- A robust STF 6mW CT ΔΣ modulator with 76dB dynamic range and 5MHz bandwidthMohammad Ranjbar, Omid Oliaei, Robert W. Jackson. 1-4 [doi]
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