Kenichi Ohhata - researchr alias

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Viewing Publication 1 - 24 from 24

2022

A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase AveragingDaiki Ogata, Ryosuke Kamiya, Yusuke Toyoshima, Kenichi Ohhata. apccas 2021: 195-198 [doi]

2021

A PVT-Robust Closed-Loop Dynamic Amplifier Using Three-Stage Floating Inverter AmplifierChiwen Cheng, Kenichi Ohhata. apccas 2021: 89-92 [doi]

2019

A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTCKenichi Ohhata. jssc, 54(7):2038-2048, 2019. [doi]

2018

A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDCKenichi Ohhata, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Kouki Ueno, Yuuki Sonoda, Kenichiro Muroya. tvlsi, 26(9):1777-1787, 2018. [doi]

A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTCKenichi Ohhata. vlsic 2018: 95-96 [doi]

Low-Power, High-Speed Time-Based Subranging ADCsKenichi Ohhata. ispacs 2018: 463-468 [doi]

2014

1-GHz, 17.5-mW, 8-bit Subranging ADC Using Offset-Cancelling Charge-Steering AmplifierKenichi Ohhata. ieicet, 97-C(4):289-297, 2014. [doi]

Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimizationKenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto. isicir 2014: 584-587 [doi]

Automatic technique of distortion compensation in resistor ladder for high-speed and low-power ADCWataru Yoshimura, Kenichi Ohhata. ieiceee, 11(11):20140313, 2014. [doi]

2011

A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical InterconnectsNorio Chujo, Toshiaki Takai, Toshiki Sugawara, Yasunobu Matsuoka, Daichi Kawamura, Koichiro Adachi, Tsuneo Kawamata, Tsuneo Ohno, Kenichi Ohhata. tcas, 58-I(9):2061-2068, 2011. [doi]

Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging TechniqueKenichi Ohhata, Hiroki Date, Mai Arita. ieicet, 94-C(12):1889-1895, 2011. [doi]

2010

A 25Gb/s laser diode driver with mutually coupled peaking inductors for optical interconnectsNorio Chujo, Tsuneo Kawamata, Kenichi Ohhata, Toshinobu Ohno. cicc 2010: 1-4 [doi]

17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnectionKenichi Ohhata, Hironori Imamura, Toshinobu Ohno, Takaya Taniguchi, Kiichi Yamashita, Toru Yazaki, Norio Chujo. iscas 2010: 1847-1850 [doi]

2009

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging ArchitectureKenichi Ohhata, Koki Uchino, Yuichiro Shimizu, Kosuke Oyama, Kiichi Yamashita. jssc, 44(11):2881-2890, 2009. [doi]

2008

Sandwich Structure Type RF-MEMS Variable Capacitor with Low Voltage Controllability and Wide Tuning RangeTakuma Nishimoto, Kiichi Yamashita, Kenichi Ohhata. ieicet, 91-B(2):572-574, 2008. [doi]

Feedthrough reduction technique for track-and-hold circuit with body-bias control circuitKenichi Ohhata, Yuichiro Shimizu, Kiichi Yamashita. ieiceee, 5(13):478-482, 2008. [doi]

2007

A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuitKenichi Ohhata, Kosuke Yayama, Yuichiro Shimizu, Kiichi Yamashita. ieiceee, 4(22):701-706, 2007. [doi]

2006

Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS TechnologyKenichi Ohhata, Katsuyoshi Harasawa, Makoto Honda, Kiichi Yamashita. ieicet, 89-C(2):203-205, 2006. [doi]

2005

SiGe-HBT-based 54-gb/s 4: 1 multiplexer IC with full-rate clock for serial communication systemsToru Masuda, Kenichi Ohhata, Nobuhiro Shiramizu, Eiji Ohue, Katsuya Oda, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Takashi Harada, Katsuyoshi Washio. jssc, 40(3):791-795, 2005. [doi]

2000

1999

A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber linksKenichi Ohhata, Toru Masuda, Kazuo Imai, Ryoji Takeyari, Katsuyoshi Washio. jssc, 34(1):18-24, 1999. [doi]

Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamic range implemented in SiGe HBTKenichi Ohhata, Toru Masuda, Eiji Ohue, Katsuyoshi Washio. jssc, 34(9):1290-1297, 1999. [doi]

1995

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAMHiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma. jssc, 30(4):491-499, April 1995. [doi]

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