Kunihiko Yamaguchi - researchr alias

researchr

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Viewing Publication 1 - 9 from 9

2000

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAMHiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma. jssc, 35(8):1159-1168, 2000. [doi]

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHzKenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta. jssc, 35(4):564-571, 2000. [doi]

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functionsTakeshi Suzuki, Keiichi Higeta, Yasuhiro Fujimura, Kazumasa Ando, Hiroaki Nambu, Ryo Yamagata, Atsuo Hotta, Kunihiko Yamaguchi. jssc, 35(2):163-174, 2000. [doi]

1998

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAMHiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Yasuhiro Fujimura, Kazumasa Ando, Takeshi Kusunoki, Kunihiko Yamaguchi, Noriyuki Homma. jssc, 33(11):1650-1658, 1998. [doi]

1995

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAMHiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma. jssc, 30(4):491-499, April 1995. [doi]

1994

1992

1989

An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAMKunihiko Yamaguchi, Hiroaki Nanbu, Kazuo Kanetani, Noriyuki Homma, Tohru Nakamura, Kenichi Ohhata, Akihisa Uchida, Katsumi Ogiue. jssc, 24(5):1390-1396, October 1989. [doi]

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