A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma. A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. J. Solid-State Circuits, 30(4):491-499, April 1995. [doi]

Abstract

Abstract is missing.