A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit

Kenichi Ohhata, Kosuke Yayama, Yuichiro Shimizu, Kiichi Yamashita. A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit. IEICE Electronic Express, 4(22):701-706, 2007. [doi]

Abstract

Abstract is missing.