Table of Contents

• A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter ModuleOliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Chua-Chin Wang. 1-5 [doi]
• A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADCXiao Han, Xiyuan Tang, Yanxing Suo, Qiao Cai, Xinzi Xu, Tianwei Wan, Yang Zhao. 1-5 [doi]
• An Eigen-decomposition Free Method for Computing Graph Fourier Transform CentralityChien-Cheng Tseng, Su-Ling Lee. 1-6 [doi]
• An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision ChipsLeyi Chen, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Cong Shi 0003, Min Tian. 1-5 [doi]
• An Accurate and Time-Efficient Subtractor by Cross Format Coding in Stochastic ComputingZhihuai Zhang, Weiqian Zhang, Shisheng Xiong, Yudi Zhao. 1-5 [doi]
• FPGA Implementation of Matrix Decomposition Based FIR FilterHao Wang, Jianyang Yan. 1-4 [doi]
• An Energy-Efficient Approximate Floating-Point Multipliers for Wireless CommunicationsJipeng Ge, Chenggang Yan 0002, Xuan Zhao, Ke Chen, Bi-Wu, Weiqiang Liu 0001. 1-5 [doi]
• An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel ReadoutDingbang Liu, Wei Mao 0002, Haoxiang Zhou, Jun Liu, Qiuping Wu, Haiqiao Hong, Hao Yu 0001. 1-5 [doi]
• Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword SpottingFeifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins. 1-5 [doi]
• Deep Texture-Depth-Based Attention for Face Recognition on IoT DevicesYuxin Lin, Wenye Liu, Chip-Hong Chang. 1-5 [doi]
• Modeling of Sneaky Hardware Trojan Using Spin-orbit Torque Assisted Magnetic Tunnel Junction for High Speed Digital CircuitsRajat Kumar, Divyanshu Divyanshu, Danial Khan, Selma Amara, Yehia Massoud. 1-5 [doi]
• An Ultra-Low-Supply Output-Capacitorless LDO with Signal- and Transient-EnhancementYajun Lin, Haozheng Wan, Jianxin Yang, Ka Nang Leung. 1-5 [doi]
• High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-KyberMinghao Li, Jing Tian 0004, Xiao Hu, Yuan Cao, Zhongfeng Wang. 1-5 [doi]
• Achieving < 1% Precision Clocking Solution with External-R under Practical ConstraintsAniruddha Roy, Preetham N. Reddy, Nitin Agarwal, Nikhil Das. 1-5 [doi]
• A Neural Recording IC Design with on-chip CMOS Electrode Array for Brain-machine InterfaceRonghao Zhang, Xu Liu 0008, Zhijie Chen, Peiyuan Wan, Tao Chen. 1-5 [doi]
• Design-Technology Co-optimization for Cryogenic Tensor Processing UnitDong Suk Kang, Shimeng Yu. 1-4 [doi]
• A 55nm 32Mb Digital Flash CIM Using Compressed LUT Multiplier and Low Power WL Voltage Trimming Scheme for AI Edge InferenceHongyang Hu, Zi Wang, Xiaoxin Xu, Kai Xi, Kun Zhang, Junyu Zhang, Chunmeng Dou. 1-5 [doi]
• A Low Noise TIA with Continuous Time-Gain Compensation for Ultrasound TransducersXinwei Yu, Fan Ye 0001, Junyan Ren. 1-4 [doi]
• A Low-latency Multi-format Carrier Phase Recovery Hardware for Coherent Optical CommunicationChanglong Lv, Liyu Lin, Honghui Deng, Junhui Wang, Yun Chen. 1-4 [doi]
• A 0.3-μA Quiescent Current Output Capacitor-Less LDO with Dynamic Slew Rate Enhance BufferTianxian Wu, Yuting Zhang, Yanhan Zeng. 1-5 [doi]
• A 40.6 ppm/°C 368 nW 10 kHz Relaxation Oscillator with Temperature-Sensor-based Piece-Wise Compensation TechniqueRuike Chen, Yaowei Ma, Yao Wang. 1-5 [doi]
• 3D Autonomous Navigation of UAVs: An Energy-Efficient and Collision-Free Deep Reinforcement Learning ApproachYubin Wang, Karnika Biswas, Liwen Zhang, Hakim Ghazzai, Yehia Massoud. 1-5 [doi]
• A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOSShuo Feng, Fuzhan Chen, Zhenghao Li, Wentao Zhou, Dongfan Xu, Chun-Zhang Chen, Xuhui Liu, HanMing Wu, Quan Pan 0002. 1-5 [doi]
• A Karnaugh Map Approximate Adder With Intrinsic Error CompensationChenyu Xie, Chunmei Yang, Hailong Jiao. 10-14 [doi]
• A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access OptimizationLiao-Chuan Chen, Zhaofang Li, Yi-Jhen Lin, Kuan-Pei Lee, Kea-Tiong Tang. 15-19 [doi]
• Key Features Selection of Power System Operation Via Improved Clustering AlgorithmXundong Gong, Yifan Zuo, Yu Zhang, Ming Chen, Haicheng Tu. 25-29 [doi]
• A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory ArchitectureHao-Wen Kuo, Rui-Hsuan Wang, Zhaofang Li, Shih-Ting Lin, Meng-Fan Chang, Kea-Tiong Tang. 30-34 [doi]
• Hierarchical DNN with Heterogeneous Computing Enabled High-Performance DNA SequencingShaobo Luo, Zhiyuan Xie, Gengxin Chen, Lei Cui, Mei Yan, Xiwei Huang, Shuwei Li, Changhai Man, Wei Mao 0002, Hao Yu 0001. 35-40 [doi]
• A 104.76-TOPS/W, Spike-Based Convolutional Neural Network Accelerator with Reduced On-Chip Memory Data Flow and Operation Unit SkippingPing-Li Huang, Chen-Han Hsu, Yu-Hsiang Cheng, Zhaofang Li, Yu-Hsuan Lin, Kea-Tiong Tang. 41-45 [doi]
• A Power Effective DLA for PBs in Opto-Electrical Neural Network ArchitectureRalph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C. H. Yu. 46-49 [doi]
• Multi-modal Asymmetric Autoencoders for Massive Photo Collection ApplicationsAymen Hamrouni, Hakim Ghazzai, Yehia Massoud. 50-54 [doi]
• An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network AcceleratorMing Liu 0022, Yifan He, Hailong Jiao. 55-59 [doi]
• Reduction of Motion Artifact in PPG signal with CDS-LMS FilterWoobean Lee, Pangi Park, SeongHwan Cho. 60-64 [doi]
• Compact Power Front-end Management for Wireless Supply of Multi-voltages to NeuromodulatorsFeng Xia 0001, Zhaoyang Zhang 0001, Jie Yang, Mohamad Sawan. 65-68 [doi]
• A 97 fJ/Conversion Neuron-ADC with Reconfigurable Sampling and Static Power ReductionJinbo Chen, Hui Wu, Jie Yang 0033, Mohamad Sawan. 73-76 [doi]
• A 6.78 MHz High-Efficiency Wireless Power Transfer Transmitter With Adaptive Dead-Time Control and Transistor-Width Switching for Implantable Medical DevicesQiang Wang, Anning Liu, Songping Mai. 77-81 [doi]
• A 0.5 to 2GHz Blocker-Tolerant Receiver Achieving 29dBm OOB-IIP3 and 3.2 to 6dB NF Using Bottom-Plate Switched-Capacitor TechniqueYi Mao, Yuyang Du, Yongjun He, Gengzhen Qi, Pui-In Mak. 82-85 [doi]
• Nanowatt High Order Analog Fully-Differential Bandpass Filter with Passive Switched-Capacitor CircuitsShiying Zhang, Xian Tang. 86-90 [doi]
• A Fast-Transient Response Capacitor-Less FVF-LDO in 22-nm CMOS TechnologyRuolin Zhou, Heng Liu, Wending Qi, Xian Tang, Songping Mai. 91-94 [doi]
• A Power-Aware ECG Transmission Framework with Server Aided Lossless CompressionJitumani Sarma, Rakesh Biswas. 95-99 [doi]
• Subpixel Interpolation Disparity Refinement for Semi-Global MatchingYunhao Ma, Xiwei Fang, Pingcheng Dong, Xinyu Guan, Ke Li, Lei Chen 0070, Fengwei An. 105-109 [doi]
• Unsupervised Image Dataset Annotation Framework for Snow Covered Road NetworksMohamed Karaa, Hakim Ghazzai, Lokman Sboui, Hichem Besbes, Yehia Massoud. 110-114 [doi]
• A 30.6-41.5uW 10-bit Column Parallel Single-Slope ADC with Minimum Voltage Feedback for CMOS Image SensorsZhoudeng Li, Xian Tang. 115-118 [doi]
• A Dynamic JPEG CODEC with Adaptive Quantization Table for Frame Storage CompressionYichen Ouyang, Xianglong Wang, Gang Shi, Lei Chen 0070, Fengwei An. 119-122 [doi]
• A 4-Channel Neural Stimulation IC Design with Charge Balancing and Exponential Current OutputJuzhe Li, Xu Liu 0008, Peiyuan Wan, Zhijie Chen. 123-127 [doi]
• A Wireless Power Design with High PCE and Fast Transient Response over a Large Loading Range for Multi-channel Neural StimulatorsWeisong Liang, Xu Liu 0008, Weijian Chen, Zeyu Lu, Peiyuan Wan, Zhijie Chen. 128-133 [doi]
• Design and Optimization of Inductive Coils for 2FSK-based Power and Data Transmission for Biomedical ImplantsWending Qi, Anning Liu, Ruolin Zhou, Songping Mai. 134-138 [doi]
• A Low-Noise Neural Signal Amplifier Achieving 1.6 NEF and 2.56 PEF for Brain-Machine InterfaceWeijian Chen, Xu Liu 0008, Weisong Liang, Zeyu Lu, Peiyuan Wan, Zhijie Chen. 144-148 [doi]
• An Energy-Efficient Readout Circuit Based on Incremental Delta-Sigma ADC with Decimation Filter for CMOS Image SensorsJunsheng Chen, Lingxin Meng, Menglian Zhao, Zhichao Tan. 149-152 [doi]
• High Linearity BJT-Based Time-Domain CMOS Temperature SensorYu Lei, Qishen Fang, Jiangchao Wu, Man Kay Law, Pui-In Mak, Rui Paulo Martins. 153-156 [doi]
• A Third-Order CIFF Noise-Shaping SAR ADC with Nonbinary Split-Capacitor DACPeng Zhang, Xiaoyong He, Shuhao Lai, Zehui Wu. 162-165 [doi]
• A 12-bit 1 GS/s Current Steering DAC with the Appointed and Thermometer Coding SchemeKo-Chi Kuo, Ying-Ju Sung. 171-175 [doi]
• A 16-Bit 2 MS/s Cyclic-pipelined ADC with Calibration for Inter-stage AmplificationJinge Ma, Yanjin Lyu, Yuanqi Hu. 176-180 [doi]
• An 8-b 8-GS/s Time-Interleaved SAR ADC With Foreground Offset Calibration in 28nm CMOSZhanpeng Yang, Xinpeng Xing, Xinfa Zheng, Haigang Feng, Hongyan Fu, Georges G. E. Gielen. 181-184 [doi]
• Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design OptimizationEric J. Wyers. 185-189 [doi]
• Design of a High Voltage Level Shift with High dV/dt Immunity and High SpeedZekun Zhou, Zhijian Zhang, Lichen Peng. 190-194 [doi]
• A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase AveragingDaiki Ogata, Ryosuke Kamiya, Yusuke Toyoshima, Kenichi Ohhata. 195-198 [doi]
• Analysis and Design of High-Speed and Low-Distortion Bootstrapped SwitchesJinge Ma, Yuanqi Hu. 199-203 [doi]
• A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDCYutong Zhao, Fan Ye 0001, Junyan Ren. 209-212 [doi]
• 0.7-6 GHz Programable Gain Push-Pull Driver PA Based on Dual-Loop BiasesMinghao Jiang, Chenyang Han, Weibo Li, Jiangfeng Wu, Yongzhen Chen. 213-216 [doi]
• Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAMSrikrishna Vasudev, Kartickraj K, Anuj Grover. 222-225 [doi]
• A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error CompensationLaimin Du, Leibin Ni, Xiong Liu, Wei Mao 0002, Hao Yu 0001. 226-230 [doi]
• Low Power and High Speed Designs of CIC Filter for Sigma-Delta ADCsZhikun He, Xinpeng Xing, Xinfa Zheng, Haigang Feng, Hongyan Fu, Georges G. E. Gielen. 236-240 [doi]
• Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel ConfigurationSae Goto, Minoru Watanabe, Nobuya Watanabe. 241-245 [doi]
• Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural NetworksXudong Wang, Geng Li, Jiacong Sun, Huanjie Fan, Yong Chen, Hailong Jiao. 246-250 [doi]
• A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS TechnologyJyoshnavi Akiri, Lean Karlo S. Tolentino, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang. 251-255 [doi]
• A High-Precision PVT-Tolerance Adaptive Clock Circuit Over Wide Frequencies in 28nm CMOSYuqiang Cui, Weiwei Shan. 256-259 [doi]
• An Energy Efficient Precision Scalable Computation Array for Neural Radiance Field AcceleratorChaolin Rao, Haochuan Wan, Yueyang Zheng, Pingqiang Zhou, Xin Lou. 260-264 [doi]
• Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment AlgorithmXuan Zhao, Chenggang Yan 0002, Chenghua Wang, Weiqiang Liu 0001. 265-269 [doi]
• SME: A Systolic Multiply-accumulate Engine for MLP-based Neural NetworkHaochuan Wan, Chaolin Rao, Yueyang Zheng, Pingqiang Zhou, Xin Lou. 270-274 [doi]
• High Precision Hysteresis Controlled MPPT Circuit for Vibration Energy HarvestingChunbiao Pan, Yidie Ye, Huakang Xia. 280-283 [doi]
• A 65-nm Clock-Domain-Crossing Controller for Digital LDO Regulator with 1.7-ns Response TimeXuliang Wang, Wing-Hung Ki, Philip K. T. Mok. 284-288 [doi]
• A 3-D Maximum Power Point Tracking Technique for Energy Harvesting System Based on Hill-Climbing AlgorithmYue Shi 0001, Zhou Gong, Jiawen Wang, Zekun Zhou, Bo Zhang 0027. 294-298 [doi]
• A Centralized Multi-String PV System Control with Multi-Dimensional MPPT ControlImran Pervez, Charalampos Antoniadis, Hakim Ghazzai, Yehia Massoud. 304-308 [doi]
• A 60V Input Integrated 3-to-1 Dual Inductor Hybrid Dickson ConverterQuyet Nguyen, Huy-Dung Han, Loan Pham-Nguyen, Hanh-Phuc Le. 309-313 [doi]
• Store, Supply, Extract and Recycle: A Boost/Buck Reconfigurable Converter for Thermal Energy HarvestingMengli Zou, Xinzi Xu, Qiao Cai, Yanxing Suo, Tianwei Wan, Jian Zhao, Yang Zhao. 314-318 [doi]
• Adaptive Line-Transient Enhancement Techniques for Dual-Path Hybrid Converter Achieving Ultra-Low Output Overshoot/UndershootHuihua Li, Qiaobo Ma, Xuchu Mu, Yang Jiang 0002, Man Kay Law, Pui-In Mak, Rui Paulo Martins. 319-323 [doi]
• A 22 mW CMOS Receiver Frontend Using Active-Feedback Baseband and Passive-Voltage Mixers Embedded in Current MirrorsBenqing Guo, Xingyue Liao, Yao Wang. 324-328 [doi]
• A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOSLeiming Wang, Xiongshi Luo, Dongfan Xu, Zhang Qiu, Yiyang Yan, Quan Pan 0002. 333-336 [doi]
• A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT ProcessWenyang Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen 0005, Shunli Ma. 337-340 [doi]
• An Approximate-Computing-Based Adaptive Equalizer for Polarization Mode DispersionLiyu Lin, Junhui Wang, Xiaoyang Zeng, Yun Chen. 346-349 [doi]
• Low-Complexity Parallel Syndrome Computation for BCH Decoders Based on Cyclotomic FFTXinyuan Qiao, Keyue Deng, Yuxing Chen, Suwen Song, Zhongfeng Wang 0001. 350-354 [doi]
• A Reconfigurable Active-RC Filter with Variable Gain and An RC-Reused Tuning CircuitShan Gao, Zhi-Jian Chen, Xiangfeng Sun, Siyuan Yang, Bin Li, Xiao-Ling Lin. 355-359 [doi]
• A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOSYihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang 0004, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen 0005, Qi Peng, Nan Qi. 360-363 [doi]
• Toward A Real-Time Elliptic Curve Cryptography-Based Facial Security SystemTuy Nguyen Tan, Hanho Lee. 364-367 [doi]
• Time Skew Calibration for Time-Interleaved Analog-to-Digital ConvertersMin Hu, Pengxing Yi, Biting Lei, Wentao Lin. 378-382 [doi]
• Design of Matrix Filter Using Discrete Cosine Transform and Path GraphChien-Cheng Tseng, Su-Ling Lee. 383-388 [doi]
• Low-Complexity Dynamic Single-Minimum Min-Sum Algorithm and Hardware Implementation for LDPC CodesQinyuan Zhang, Suwen Song, Zhongfeng Wang. 389-393 [doi]
• A High-speed Event-based Object Tracking with Heterogeneous Computing HardwareChenyang Shi, Jing Jin, Boyi Wei, Yuzhen Li, Wenzhuo Li, Hanxiao Liu, Yibo Zhang, Shaobo Luo. 394-399 [doi]
• Emotion Recognition of Physical Activities for Health Monitoring Using Machine LearningKai Sun, Jihong Zhu, Jie Liang. 400-403 [doi]
• Optimal Evasive Path Planning with Velocity ConstraintKarnika Biswas, Hakim Ghazzai, Indrani Kar, Yehia Massoud. 409-413 [doi]
• Thermometer Code of Log Mel-Frequency Spectral Coefficient for BNN-based Keyword Spotting SystemYuzhong Jiao, Yiu Kei Li, Chi-Hong Chan, Yun Li, Zhilin Ai. 414-418 [doi]
• Fast Responsive Framework for Optimal Power Flow Analysis in Power SystemXundong Gong, Jinyue Lu, Shaolei Zong, Ming Chen, Yongxiang Xia. 419-423 [doi]
• Chaotic Sampling of Double Scroll Chaos for Digital Random Number GenerationOnur Karatas, Kaya Demir, Salih Ergün. 424-427 [doi]
• Autoencoder-Based Anomaly Detection for Time Series Data in Complex SystemsXundong Gong, Shibo Liao, Fei Hu, Xiaoqing Hu, Chunshan Liu. 428-433 [doi]
• Change Point Detection for Time Series Data in Complex SystemsXundong Gong, Jia Ma, Ming Chen, Shaolei Zong, Chunshan Liu. 434-438 [doi]
• Bitwise Logical Operations in VCMA-MRAMGulafshan Gulafshan, Rajat Kumar, Danial Khan, Selma Amara, Yehia Massoud. 439-443 [doi]
• Quantum Efficiency Enhancement in Si Avalanche Photodiodes in the NIR Regime via Surface Texturing Towards Autonomous Driving ApplicationsYiyang Zhang, Tianyi Wang, Jun Lan, Wenhui Wang, Longyang Lin, Yida Li. 444-448 [doi]
• Simulation of Gap Structure Optical Waveguide with Phase Change MaterialsJinxuan Liang, Zhuoxuan Zhu, Yida Dong, Lei Lei, Yida Li, Mei Shen, X.-D. Xiang. 454-457 [doi]
• Logic Locking for Hardware Security Using Voltage-Gated Spin-orbit Torque Magnetic Tunnel JunctionDivyanshu Divyanshu, Rajat Kumar, Danial Khan, Selma Amara, Yehia Massoud. 458-462 [doi]
• th-Order Gain-Boosted N-Path LNAZhixiang Liu, Shiyou Wei, Gengzhen Qi, Pui-In Mak. 463-467 [doi]
• A 300-GHz Wideband Injection Locked Frequency Quadrupler in 250-nm InP DHBT TechnologySurajit Kumar Nath, Daekeun Yoon. 468-471 [doi]
• A Hybrid Method for Signal Probability Estimation with Combinational CircuitsChunhong Chen, Suoyue Zhan. 472-475 [doi]
• Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAsJianwen Luo 0004, Xinzhe Liu, Fupeng Chen, Yajun Ha. 476-480 [doi]
• An Improved Multi-Objective Optimization Framework for Soft-Error Immune CircuitsShaohang Chu, Yan Li, Xu Cheng, Xiaoyang Zeng. 481-484 [doi]
• "Fusion, Interaction, and Training": Cultivating Innovative Leading TalentsHua Fan 0001, Kaicong Dong, Xiuhua Xie, Quanyuan Feng, Qiang Hu. 485-488 [doi]
• Implementation of a Training Computer Program for Circuit Analysis in the Time DomainAleksandr Kornilov. 489-492 [doi]
• A Quantization Model Based on a Floating-point Computing-in-Memory ArchitectureXi Chen, An Guo, Xinbing Xu, Xin Si, Jun Yang. 493-496 [doi]
• RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge InferenceLinfang Wang, Junjie An, Wang Ye, Weizeng Li, Hanghang Gao, Yangu He, Jianfeng Gao, Jinshan Yue, Lingyan Fan, Chunmeng Dou. 497-500 [doi]
• A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN AcceleratorsYongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang. 501-504 [doi]
• Pipelined Computing-in-Memory Macro with Computation-Memory Aware TechniqueLiang Chang, Pan Zhao, Jun Zhou. 505-509 [doi]
• A Reliable and Economical Test Method for Semiconductor Device AgingXinhuan Yang, Qianqian Sang, Chuanzheng Wang, Shuo Wang, Liang Wang, Yuanfu Zhao. 520-523 [doi]
• A Booth-based Digital Compute-in-Memory Marco for Processing Transformer ModelZhongyuan Feng, Bo Wang, Zhaoyang Zhang, An Guo, Xin Si. 524-527 [doi]
• Total Dose and Single Event Effects on 16 Mbit Standalone Spin-Transfer Torque MRAM with 45 nm CMOS TechnologyAnni Cao, Xin Li, Liang Wang, Jianpeng Zhang, Chunliang Gou, Liquan Liu, Bi Wang, Xing Zhang, Yuanfu Zhao. 528-531 [doi]
• The Synergetic Effects of Total Ionizing Dose and High Temperature on 180 nm DSOI TechnologyXu Zhang, Fanyu Liu, Bo Li 0051, Siyuan Chen, Yang Huang, Jiangjiang Li, Jian Jiao, Tianchun Ye, Jiajun Luo. 532-535 [doi]
• Design of Integrated Circuit Hard Defect Location System Based on Thermal Laser StimulationWenjian Wu, Yingqi Ma, Minghui Cai. 536-540 [doi]
• Hardware-Aware Quantization for Multiplierless Neural Network ControllersTobias Habermann, Jonas Kühle, Martin Kumm, Anastasia Volkova. 541-545 [doi]
• FPGA Implementation of N-BEATS for Time Series Forecasting Using Block Minifloat ArithmeticWenjie Zhou, Haoyan Qi, David Boland, Philip H. W. Leong. 546-550 [doi]
• Frequency-Selective Limiting Using Automatic Gain Control of Stagger-Tuned N-Path FiltersM. Mahmudul Hasan Sajeeb, Loai G. Salem. 551-555 [doi]
• 26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path LoopZhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu, Yong Chen 0005, Zhao Zhang 0004. 556-559 [doi]
• A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAEZhiyang Zhang, Xi Wang, Yong Chen 0005, Junyan Ren, Shunli Ma. 560-564 [doi]
• A 28GHz Current-mode Outphasing Power Amplifier with 23.3dBm Psat and 44.2% PAE in 40nm CMOSHao Wang, Zhongka Lin, Kaiming Zhong, Xiang Yi, Guangyin Feng, Yanjie Wang. 565-568 [doi]
• 2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLLYixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu, Yong Chen 0005, Zhao Zhang 0004. 569-573 [doi]
• A 27-29.5GHz 6-Bit Phase Shifter with 0.67 -1.5 degrees RMS Phase Error in 65nm CMOSQin Duan, Zhi-Jian Chen, Fengyuan Mao, Yu Zou, Bin Li, Guangyin Feng, Yanjie Wang, Xiao-Ling Lin. 574-577 [doi]
• Multi-type SRAM Test Structure with an Improved March LR AlgorithmXinshun Ning, Hongyong Yang, Mengdi Zhang, Yanji Wang, Ye Zhao, Shushan Qiao. 578-582 [doi]
• Design of SEL Self-Recovery Hardness for 90nm COTS Devices Using R-C-S Network with DC-DC ConverterJindou Xin, Xiang Zhu, Yingqi Ma, Jianwei Han. 583-587 [doi]
• Study on Single Event Burnout Effect for 18V LDMOS Based on 0.18µm Process TechnologyLangtao Chen, Xin Zhou, Ying Wang, Ying Kong, Rubin Xie, Ling Peng, Yantu Mo, Ming Qiao, Bo Zhang. 588-591 [doi]
• A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber AlgorithmHonglin Kuang, Yifan Zhao, Jun Han. 592-595 [doi]
• A High Throughput and Configurable Pseudo-random Number Extension Generator for Lattice-based Post-quantum CryptographyXiang Li, Dongsheng Liu, Ang Hu, Aobo Li, Shuo Yang, Jiahao Lu, Jianming Lei. 596-600 [doi]
• Lightweight and Efficient Hardware Implementation for Saber Using NTT MultiplicationTianyu Xu, Yijun Cui, Dongsheng Liu, Chenghua Wang, Weiqiang Liu 0001. 601-605 [doi]
• High Efficient Architecture of Polynomial Multiplier with Variable Parameter Based on 2KNTTHui-Qin Li, Tao Chen, Ai-qing Wu, Chao-xing Xu, Wei Li, Longmei Nan. 606-610 [doi]
• Better Security Estimates for Approximate, IoT-Friendly R-LWE CryptosystemsRuth O'Connor, Ayesha Khalid, Máire O'Neill, Weiqiang Liu 0001. 611-615 [doi]