A 16-Bit 2 MS/s Cyclic-pipelined ADC with Calibration for Inter-stage Amplification

Jinge Ma, Yanjin Lyu, Yuanqi Hu. A 16-Bit 2 MS/s Cyclic-pipelined ADC with Calibration for Inter-stage Amplification. In IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022. pages 176-180, IEEE, 2022. [doi]

Abstract

Abstract is missing.