Ralph Gerard B. Sangalang - researchr alias

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Viewing Publication 1 - 13 from 13

2023

FPGA-Based Radio Transceiver Using the TV White Space for Disaster Response OperationKhryzz Lyden G. Cueto, Ricky Mae V. Santos, Claudette Jane C. Hilario, John Carl V. Aggari, Ralph Gerard B. Sangalang. icitjo 2023: 300-304 [doi]

Developing an LTE Learning Material: Experiences from a University in a Developing CountryLeinard C. Lontoc, Marjorie H. Basco, Vannesa Ann P. Sulit, Genesis Aubrey M. Magpantay, Mirasol C. Dilay, Ralph Gerard B. Sangalang. icitjo 2023: 295-299 [doi]

A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS ProcessRalph Gerard B. Sangalang, Shih-Heng Luo, Chua-Chin Wang. icicdt 2023: 64-67 [doi]

Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOSRalph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang. asicon 2023: 1-5 [doi]

A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS ProcessRalph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang. tcasII, 70(10):3862-3866, October 2023. [doi]

A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead AdderChua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee. cssp, 42(4):2283-2304, April 2023. [doi]

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS processChua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang. integration, 90:245-260, May 2023. [doi]

A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS processChua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose. iet-cds, 17(2):75-87, March 2023. [doi]

2022

2021

A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction CircuitChua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng. tcasII, 68(12):3478-3482, 2021. [doi]

An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOSChua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee. mj, 118:105295, 2021. [doi]

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