Table of Contents

• A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOsMayank Kumar Singh, Manish Kumar Gautam, Puneet Singh, R. Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare. 1-5 [doi]
• A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental SpurSoumith Kusumanchi, Srinivas Theertham, Arpan Thakkar, Nagendra Krishnapura. 6-10 [doi]
• Settling Time Reduction in a Phase-Locked Loop using Pre-emphasisSumit Kumar, Nagendra Krishnapura. 11-15 [doi]
• A 1-6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOSRaviteja Kammari, Sarvesh Rajesh Tuckely, Vijay Shankar Pasupureddi. 16-20 [doi]
• Energy Efficient DSHE based Analogue Multiply Accumulate Computing Crossbar ArchitectureSandeep Soni, Gaurav Verma, Alok Kumar Shukla, Brajesh Kumar Kaushik. 21-25 [doi]
• Investigation of Voltage Fault Injection Attacks on NN Inference Utilizing NVM Based Weight StorageSupriya Chakraborty, Tamoghno Das, Manan Suri. 26-30 [doi]
• A Bio-Inspired CMOS Circuit for the Excitation and Inhibition of Neuronal OscillatorsBharath Kumar Singh Muralidhar, Bakr Al Beattie, Max Uhlmann, Karlheinz Ochs, Gerhard Kahmen, Robert Rieger. 31-35 [doi]
• FPGA Implementation of Inversion in Galois Field Over GF(2m) with FLT and ITA Using Quad BlocksVemanaboina Vamsi, Kishor Sarawadekar. 36-39 [doi]
• An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence AlignmentAjay S, Praveen V. S, Kuruvilla Varghese. 40-44 [doi]
• Ternary Systolic Array Architecture for Matrix Multiplication in CNFET-Memristor TechnologyShivani Thakur, Srinivasu Bodapati. 45-49 [doi]
• A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS ProcessRalph Gerard B. Sangalang, Wei-Zhen Chen, Chua-Chin Wang. 50-54 [doi]
• True Random Number Generator Implemented in ReRAM Crossbar Based on Static Stochasticity of ReRAMsTanay Patni, Abhijit Pethe. 55-59 [doi]
• Digital to Pulse Converter for Analog in Memory Compute ApplicationsSanmitra Bharat Naik, Asif Iqbal. 60-64 [doi]
• Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGANoble G, Nalesh S 0001, S. Kala. 65-69 [doi]
• Passive RF Resonant Receiver with Voltage Gain for Wireless Power Transfer SystemVikas Kumar, Santosh Parajuli, Shivansh Awasthi, Gayatri Ranade, Kartik Tyagi, Saheli Roy Chowdhury, Rahul Jaiswal, Thomas George Thundat, Ankur Gupta. 70-74 [doi]
• tinyRadar for Gesture Recognition: A Low-power System for Edge ComputingDileep Kankipati, Madhu Munasala, Dasari Sai Nikitha, Satyapreet Singh Yadav, Sandeep Rao, Chetan Singh Thakur. 75-79 [doi]
• Novel Label Flipping Dataset Poisoning Attack Against ML-Based HT Detection SystemsRicha Sharma, G. K. Sharma 0001, Manisha Pattanaik. 80-84 [doi]
• LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic LockingJugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey. 85-89 [doi]
• Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFETJyoti Patel, Govind Sharma 0007, Chitraja Rajan, Vivek Kumar, Sudeb Dasgupta. 90-94 [doi]
• Power-Efficient Approximate Multipliers Leveraging Hybrid CMOS-Memristor ParadigmMonika Pokharia, Ravi S. Hegde, Joycee Mekie. 95-99 [doi]
• ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage ApplicationsRavi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu. 100-104 [doi]
• An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV RegimeMahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu. 105-109 [doi]
• Reinforcement Learning Based Prefetch-Control MechanismSoma Niloy Ghosh, Vineet Sahula, Lava Bhargava. 110-114 [doi]
• Comparative Analysis of SPAD Models for Low-Light ImagingHarshith Nimmagadda, Anshu Sarje. 115-119 [doi]
• Implementation and Comparative Analysis of Flexible Micro-Heater Circuits for Lab-on-a-chip ApplicationsAnjali Singh, Vikranth Varma Kosuri, Anshu Sarje. 120-124 [doi]
• A High-Impedance 3-MOSFET Pseudo-Resistor for Instrumentation Amplifiers of Biomedical SensorsFeng Yan, Kangkang Sun, Zhipeng Li, Jian Guan, Bingjun Xiong, Jingjing Liu. 125-128 [doi]
• Deep Learning Based Portable Respiratory Sound Classification SystemAdithya Sunil Edakkadan, Abhishek Srivastava 0002. 129-133 [doi]
• A Self-Biased Subthreshold CMOS Voltage Reference with Temperature Compensation Circuit for IoT Self-Powered Sensor ApplicationsYuxuan Huang, Feng Yan, Kangkang Sun, Jingjing Liu. 134-138 [doi]
• A 197 dBc/Hz FoMT 24.8-28.97 GHz Class-F VCO Using Single-Turn Multi-Tap InductorAnik Batabyal, Rajesh Zele. 139-143 [doi]
• Analysis of Switched-RC N-path filters with Finite Switch Resistance and Switched $G_{m}-C$ filters using the Adjoint NetworkEndersh Soni, Saravana Manivannan. 144-148 [doi]
• A Low-Loss, Compact Wideband True-Time-Delay Line for Sub-6GHz Applications Using N - Path FiltersMohmad Aasif Bhat, Imon Mondal. 149-153 [doi]
• Modified Gm-Free Assisted Opamp Technique in Continuous Time Delta Sigma ModulatorsSayan Banerjee, Ankesh Jain. 154-158 [doi]
• Low Precision Floating Point Spectral Feature Extraction Engine for Closed-Loop NeuromodulationSagar Mahajan, Poulami Mandal, Laxmeesha Somappa. 159-163 [doi]
• Noise Efficient Three-Channel Amplifier for MEMS Cantilever ReadoutSebastian Simmich, Patrick Wiegand, Robert Rieger. 164-168 [doi]
• Sensor Node with Position Validation towards Camptocormia Measurement at HomeKamran Naderi Beni, Matthias Christoph Eger, Nils G. Margraf, Robert Rieger. 169-172 [doi]
• Implementation of FFT Using Low-Precision Floating Point for Rapid High Precision MEMS ReadoutsHitesh Sahu, Emon Sarkar, Laxmeesha Somappa. 173-177 [doi]
• Efficient CORDIC Architectures for FFT Based All Digital Resonator Frequency EstimationPushkar Sathe, Ajay Verma, Laxmeesha Somappa. 178-182 [doi]
• A Novel Low-Power Shift-Register Controller for Digital Low-Dropout RegulatorsKartikay Mani Tripathi, Madhav Pathak, Sanjeev Manhas, Anand Bulusu. 183-187 [doi]
• A 95-nA Quiescent-Current Fast-Transient Output-Capacitor-Less LDO with Enhanced Load Regulation for IoT ApplicationsRaghav Bansal, Shouri Chatterjee. 188-192 [doi]
• A Novel Architecture with Nullified Parasitic Capacitance for Accurate FuSa DetectionAnup J. Deka, Biswarup Rana, Shuvoshree Bhattacharya. 193-196 [doi]
• Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler ElectronicsNishant Kumar, Hari Shanker Gupta, Nilesh M. Desai, Nihar Ranjan Mohapatra. 197-201 [doi]
• A Transient-Enhanced Capacitor-Less LDO With 30-MHz Bandwidth and High Slew RateWangchen Fan, Zhongyuan Fang, Yongjia Lil, Minggang Chen, Weifeng Sun. 202-206 [doi]
• Large Network of Wide- Range Analog Voltage Observers for Debug & TestabilityTapas Nandy, Ashish Joshi, Sanjoy Kumar Dey. 207-211 [doi]
• Efficient Dilution of a Fluid from its Related Arbitrary Stock Solutions using MEDA BiochipsSurya Naga Aditya V. Dupukuntla, Koushik Sai Nimmaturi, Tamal Mandal, Sathwik Abramoni, Sudip Roy 0001. 212-216 [doi]
• An 8-Channel TDM Spectral Feature Extraction for Neuromodulation SoCK. Akhilesh Rao, Laxmeesha Somappa. 217-221 [doi]
• V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal SimulationYicong Shao, Chao Wang, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao 0004, Wei Mao, Yongfu Li 0002. 222-226 [doi]
• Exploiting Node Level Algorithm Diversity for Distributed Compressed SensingKetan Atul Bapat, Mrityunjoy Chakraborty. 227-231 [doi]
• Architectural Exploration of Heterogeneous FPGAs for Performance Enhancement of ML BenchmarksAnubhav Mishra, Nanditha Rao, Ganesh Gore, Xifan Tang. 232-235 [doi]
• Multiplexer & Memory Efficient Bit-Reversal AlgorithmsBasamgari Bhanu Prakash Reddy, Nitish Kumar, Kavindra Kandpal, Manish Goswami. 236-240 [doi]
• A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAsZainab Aizaz, Kavita Khare, Mohd Anas Khan, Mahesh Kumar Singh, Dhandapani Vaithiyanathan. 241-245 [doi]
• 2MOS ApplicationTika Ram Pokhrel, Alak Majumder. 246-250 [doi]
• stOrder $\Sigma\Delta$ ADCAshish Joshi, Tapas Nandy, Aashish T. R, Mayank Devam, Sanjoy Kumar Dey. 251-255 [doi]
• A 0.6V 10-bit 20kHz Capacitor Splitting Bypass Window SAR ADC for Biomedical ApplicationsKangkang Sun, Feng Yan, Huan Wu, Jingjing Liu. 256-260 [doi]
• Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory ComputingBipul Boro, Ashvinikumar Dongre, Rushik Parmar, Gaurav Trivedi. 261-265 [doi]
• 2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETsOliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Jui-Min Kuo, Mitch Ming-Chi Chou, Chua-Chin Wang. 266-270 [doi]
• A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS ProcessJhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang. 271-275 [doi]
• High-Precision Open-Loop Time Amplifier Using Current RegulatorYusuke Toyoshima, Ryosuke Kamiya, Kenichi Ohhata. 276-279 [doi]
• A Robust Overdesign Prevention Circuit Technique Under Widely Varying Ambient ConditionsMayank Anupam, Imon Mondal. 280-284 [doi]
• Radial Basis Function Based Surrogate-Assisted Metaheuristic Approach for Variability AnalysisJoel Thomas, Jai Narayan Tripathi. 285-288 [doi]
• On Edge FPN Reduction in CMOS Image Sensor Using CNN with Attention MechanismSandeep Kodam, Wilfred Kisku, Amandeep Kaur 0005, Deepak Mishra 0003. 289-293 [doi]
• CAWPR: Contention Aware Write Preemptive Management Policy for Hybrid Last Level CachesSwatilekha Majumdar. 294-298 [doi]
• Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized DesignsLakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi. 299-303 [doi]
• A Cryogenic Voltage Regulator with Integrated Voltage Reference in 22 nm FDSOI TechnologyA. R. Cabrera-Galicia, A. Ashok, Patrick Vliex, Andre Kruth, Andre Zambanini, Stefan van Waasen. 304-308 [doi]
• High Throughput Hardware Acceleration for Image Generation using HLSA. BhanuPrasad, Kuruvilla Varghese. 309-313 [doi]
• An Intelligent CMOS Image Sensor System Using Edge Information for Image ClassificationWilfred Kisku, Prateek Khandelwal, Amandeep Kaur 0005, Deepak Mishra 0003. 314-318 [doi]
• ECG Artifacts Suppression Using the NLSRA-Based Cascaded Fixed Point Interference CancellerMohammed Mujahid Ulla Faiz, Azzedine Zerguine, Izzet Kale. 319-322 [doi]
• A MATE-GDBF Algorithm for Irregular Punctured LDPC Codes and Its Decoder ImplementationXiao-Juan Huang, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang, Sau-Gee Chen. 323-327 [doi]
• Energy Harvester Powered Fully Digital ECG Front End Acquisition with Integrated TDCBiswajit Mishra, Purvi Patel. 328-332 [doi]
• NDIE: A Near DRAM Inference Engine Exploiting DIMM's ParallelismPalash Das, Hemangee K. Kapoor. 333-337 [doi]
• All Digital Minimum Energy Point Detection for Ultra Low Power CMOS CircuitsPurvi Patel, Biswajit Mishra. 338-342 [doi]
• Efficient Hardware Design of Parameterized Posit Multiplier and Posit AdderSadhu Sai Ram, Kuruvilla Varghese. 343-347 [doi]
• Real-Time Zero-Phase Digital Filter Using Recurrent Neural NetworkTantep Sinjanakhom, Sorawat Chivapreecha. 348-352 [doi]
• Design and Characterization of Quantum Cellular Automata (QCA) Based Optimized Circuits for Emerging TechnologiesSourav Karmakar, Anshu Sarje, Aftab M. Hussain. 353-357 [doi]
• Design of a Wideband 8-20 GHz Receiver Front-End with Reduced Local Oscillator Phase-Error in 4-Path MixerArpit Sahni, Abhishek Srivastava 0002. 358-362 [doi]
• Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAsMayur S. Marinaik, Naveen Kadayinti. 363-366 [doi]
• On a Piecewise Linear Function Approximation for Quantum ComputationHideaki Okazaki. 367-370 [doi]
• A 0.9V Current-Mode Bandgap Reference with Wideband PSRR Better than 70dB from -40°C to 75°CS. Tarun Varma, Krishna Kanth Avalur. 371-374 [doi]
• An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS RangeSandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy. 375-377 [doi]