Kavita Khare - researchr alias

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Viewing Publication 1 - 24 from 24

2023

ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAsZainab Aizaz, Kavita Khare. tcasII, 70(12):4569-4573, December 2023. [doi]

FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning ApplicationsZainab Aizaz, Kavita Khare, Aizaz Tirmizi. fccm 2023: 210 [doi]

2022

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error CompensationZainab Aizaz, Kavita Khare. tcasII, 69(2):579-583, 2022. [doi]

Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation errorZainab Aizaz, Kavita Khare. ijcta, 50(6):2252-2270, 2022. [doi]

2021

A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization TechniqueDivya Gautam, Kavita Khare, Bhavana P. Shrivastava. access, 9:44436-44441, 2021. [doi]

2019

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET TechnologyAjay Kumar Dadoria, Kavita Khare. cssp, 38(9):4338-4356, 2019. [doi]

2018

New Leakage Reduction Techniques for FinFET Technology with Its ApplicationAjay Kumar Dadoria, Kavita Khare, Tarun Kumar Gupta, R. P. Singh. jcsc, 27(7):1-23, 2018. [doi]

2016

Concept, Design, and Implementation of Reconfigurable CORDICSupriya Aggarwal, Pramod Kumar Meher, Kavita Khare. tvlsi, 24(4):1588-1592, 2016. [doi]

Leakage Power Reduction Technique by using FinFET TechnologyAjay Kumar Dadoria, Kavita Khare, R. P. Singh. ictcs2 2016: [doi]

Low-Power High Speed 1-bit Full Adder Circuit DesignShailesh Dwivedi, Kavita Khare, Ajay Kumar Dadoria. ictcs2 2016: [doi]

2013

CORDIC-based window implementation to minimise area and pipeline depthSupriya Aggarwal, Kavita Khare. iet-spr, 7(5):427-435, 2013. [doi]

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform GenerationSupriya Aggarwal, Pramod Kumar Meher, Kavita Khare. tcas, 60-I(2):314-326, 2013. [doi]

Leading One Detection Hyperbolic CORDIC with Enhanced Range of ConvergenceSupriya Aggarwal, Kavita Khare. vlsisp, 70(1):49-57, 2013. [doi]

Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC PipelineSupriya Aggarwal, Kavita Khare. vlsid 2013: 60-65 [doi]

Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino CircuitsTarun K. Gupta, Kavita Khare. cssp, 32(6):2707-2722, 2013. [doi]

3D CORDIC Algorithm Based Cartesian to Spherical Coordinate ConverterAnita Jain, Kavita Khare. vdat 2013: 337-344 [doi]

2012

2011

VCAT synchroniser - reduction of buffer size in VCAT enabled next generation SDH networksSunanda Manke, Kavita Khare, S. D. Sapre. ett, 22(8):500-514, 2011. [doi]

2009

Differential Delay Compensator -- A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH NetworksSunanda Manke, Kavita Khare, S. D. Sapre. artcom 2009: 244-248 [doi]

2008

100Mbps Ethernet data transmission over SDH networks using Cross Virtual ConcatenationSunanda Manke, Kavita Khare, S. D. Sapre. icon 2008: 1-6 [doi]

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