Table of Contents

• Keynote Talk: A History of the VLSI Design ConferenceVishwani D. Agrawal. 1-2 [doi]
• Keynote Talk: Semiconductor Industry: Best of Times, Worst of Times, and Nowhere Else I Would Rather Be!Jaswinder S. Ahuja. 3-4 [doi]
• Keynote Talk: A Wireless Sensor a Day Keeps the Doctor AwayBert Gyselinckx. 5-6 [doi]
• Keynote Talk: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing MachinesRajesh Gupta. 7-8 [doi]
• Keynote Talk: Challenges in Automotive Cyber-physical Systems DesignSamarjit Chakraborty. 9-10 [doi]
• Tutorial T1: Design of Mixed-Signal Systems using SystemC AMS ExtensionsSumit Adhikari, Markus Damm, Christoph Grimm, François Pêcheux. 11-12 [doi]
• Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in FutureHimanshu Thapliyal, Nagarajan Ranganathan. 13-15 [doi]
• Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product YieldSrikanth Venkataraman, Nagesh Tamarapalli. 16-17 [doi]
• Tutorial T4: Intellectual Property Protection and Security in System-on-Chip DesignSusmita Sur-Kolay, Swarup Bhunia. 18-19 [doi]
• Tutorial T5: Advanced Analog-Mixed Signal System and Circuit TechniquesPavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez. 20-21 [doi]
• Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale ComputingNikil Dutt, Mani B. Srivastava, Rajesh Gupta, Subhasish Mitra. 22-24 [doi]
• Tutorial T7A: New Modeling Methodologies for Thermal Analysis of 3D ICs and Advanced Cooling Technologies of the FutureDavid Atienza, Arvind Sridhar. 25-26 [doi]
• Tutorial T7B: Optimally Addressing Verification Constraint Complexity for Effective Functional ConvergenceShankar Hemmady. 27 [doi]
• Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore SystemsAjay Joshi. 28 [doi]
• Tutorial T8B: Wireless System Design and Systems Engineering ChallengesKameswara Rao B., Muralidhar Reddy B., Ravi Kishore B.. 29-30 [doi]
• Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial OverviewAnnajirao Garimella, Punith R. Surkanti, Paul M. Furth. 31-32 [doi]
• Embedded Tutorial ET2: Digital Subscriber LineM. Kalyana Kumar Rao, Shantha Kumari P. V., Boopalan Sellappan. 33-34 [doi]
• Embedded Tutorial ET3: Packaging Trends, Die Package Co-Design Flow and ChallengesSiva Kothamasu. 35 [doi]
• Embedded Tutorial ET4: Advanced Techniques for Programming Networked Embedded SystemsVijay Raghunathan. 36-37 [doi]
• Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere?Sathyam K. Pattanam, P. P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, Vikas Gautham, Raju Bala Showry Pudota. 38 [doi]
• Random Access Analog Memory (RA2M) for Video Signal ApplicationNilanjan Chattaraj, Anindya Sundar Dhar. 39-44 [doi]
• A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADCManas Kumar Hati, Tarun Kanti Bhattacharyya. 45-50 [doi]
• A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio ApplicationsSaravana Kumar, Shouri Chatterjee. 51-56 [doi]
• Hardware Efficient Architecture for Generating Sine/Cosine WavesSupriya Aggarwal, Kavita Khare. 57-61 [doi]
• Power Aware Hardware Prototyping of Multiclass SVM Classifier Through ReconfigurationRajesh A. Patil, Gauri Gupta, Vineet Sahula, A. S. Mandal. 62-67 [doi]
• A High Speed FIR Filter Architecture Based on Novel Higher Radix AlgorithmS. K. Sahoo, K. Srinivasa Reddy. 68-73 [doi]
• Impact of Body Bias Based Leakage Power Reduction on Soft Error RateWarin Sootkaneung, Kewal K. Saluja. 74-79 [doi]
• An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMsAnkur Goel, Donald Evans, Richard Stephani, Venkateswara Reddy, Dharmendra Rai, Veerabadra Chary, N. Sathisha. 80-84 [doi]
• An Energy Efficient Oscillator Frequency Calibration Methodology Using Fraction Phase ComputationAmitava Ghosh, Isha Das, Achintya Halder. 85-91 [doi]
• Self-Induced Supply Noise Reduction Technique in GBPS Rate TransmittersNitin Gupta, Tapas Nandy, Phalguni Bala. 92-95 [doi]
• Buffer Design and Eye-Diagram Based Characterization of a 20 GS/s CMOS DACMohit Singh, Shalabh Gupta. 96-100 [doi]
• Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOSPawan Kumar Moyade, Nandakumar Nambath, Allmin Ansari, Shalabh Gupta. 101-106 [doi]
• HD Resolution Intra Prediction Architecture for H.264 DecoderJimit Shah, K. S. Raghunandan, Kuruvilla Varghese. 107-112 [doi]
• Design for Security of Block Cipher S-Boxes to Resist Differential Power AttacksBodhisatwa Mazumdar, Debdeep Mukhopadhyay, Indranil Sengupta. 113-118 [doi]
• Real-time Melodic Accompaniment System for Indian Music Using TMS320C6713Prateek Verma, Preeti Rao. 119-124 [doi]
• Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power ManagementSujan K. Manohar, Vinod K. Somasundar, Ramakrishnan Venkatasubramanian, Poras T. Balsara. 125-130 [doi]
• Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial OverviewAnnajirao Garimella, Punith R. Surkanti, Paul M. Furth. 131-136 [doi]
• 3-D Parasitic Modeling for Rotary InterconnectsVinayak Honkote, Ankit More, Baris Taskin. 137-142 [doi]
• Power Aware Post-Manufacture Tuning of MIMO Receiver SystemsDebashis Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee. 143-148 [doi]
• GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio ApplicationsDhiraj Reddy Nallapa Yoge, Nitin Chandrachoodan. 149-154 [doi]
• Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal ManagementJunyoung Park, H. Mert Ustun, Jacob A. Abraham. 155-160 [doi]
• Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded SystemsZhe Wang, Sanjay Ranka, Prabhat Mishra. 161-166 [doi]
• Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM ArchitecturesCory E. Merkel, Dhireesha Kudithipudi. 167-172 [doi]
• CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance SpectroscopyPramod Murali, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy. 173-178 [doi]
• A Compact Temperature Sensor at 1.8µA per Hz Conversion Rate and 1.1 °C Accuracy for SOCsSubhajit Sen, Dan Babitch, Noshir Dubash. 179-184 [doi]
• Analysis of the Pull-In Phenomenon in Microelectromechanical VaractorsAnindya Lal Roy, Anirban Bhattacharya, Ritesh Ray Chaudhuri, Tarun Kanti Bhattacharyya. 185-190 [doi]
• Low-Latency No-Handshake GALS Interfaces for Fast-Receiver LinksJean-Michel Chabloz, Ahmed Hemani. 191-196 [doi]
• Set-Cover Heuristics for Two-Level Logic MinimizationAnkit Kagliwal, Shankar Balachandran. 197-202 [doi]
• A Rapid Methodology for Multi-mode Communication Circuit GenerationLiang Tang, Jorgen Peddersen, Sri Parameswaran. 203-208 [doi]
• An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip ChargerMahima Arrawatia, Varish Diddi, Harsha Kochar, Maryam Shojaei Baghini, Girish Kumar. 209-214 [doi]
• Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting SystemsChao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy. 215-220 [doi]
• Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power EfficiencySujan K. Manohar, Ramakrishnan Venkatasubramanian, Poras T. Balsara. 221-226 [doi]
• A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic BiochipRitwik Mukherjee, Hafizur Rahaman, Indrajit Banerjee, Tuhina Samanta, Parthasarathi Dasgupta. 227-232 [doi]
• Clock Tree Skew Minimization with Structured RoutingPinaki Chakrabarti. 233-237 [doi]
• Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface MethodologySourindra Chaudhuri, Prateek Mishra, Niraj K. Jha. 238-244 [doi]
• Real-Time, Content Aware Camera - Algorithm - Hardware Co-Adaptation for Minimal Power Video EncodingJoshua W. Wells, Jayaram Natarajan, Abhijit Chatterjee, Irtaza Barlas. 245-250 [doi]
• Way Sharing Set Associative Cache ArchitectureC. J. Janraj, T. Venkata Kalyan, Tripti Warrier, Madhu Mutyam. 251-256 [doi]
• A Novel Encoding Scheme for Low Power in Network on Chip LinksDeepa N. Sarma, Gopalakrishnan Lakshminarayanan, K. V. R. Suryakiran Chavali. 257-261 [doi]
• A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage IslandsNishit Ashok Kapadia, Sudeep Pasricha. 262-267 [doi]
• A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-ChipSudeep Pasricha. 268-273 [doi]
• An Ultra-low Power Symbol Detection Methodology and Its Circuit Implementation for a Wake-up Receiver in Wireless Sensor NodesDeepak Kumar Meher, Arunkumar Salimath, Achintya Halder. 274-279 [doi]
• Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCsChetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. 280-285 [doi]
• A 1.25GHz 0.8W C66x DSP Core in 40nm CMOSRaguram Damodaran, Timothy Anderson, Sanjive Agarwala, Rama Venkatasubramanian, Michael Gill, Dhileep Gopalakrishnan, Anthony M. Hill, Abhijeet Chachad, Dheera Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, Shriram Moharil, Matthew Pierson, Steven Mullinnix, Hung Ong, David Thompson, Krishna Gurram, Oluleye Olorode, Nuruddin Mahmood, Jose Flores, Arjun Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman. 286-291 [doi]
• A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-ChipPraveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar. 292-297 [doi]
• Efficient Online RTL Debugging Methodology for Logic Emulation SystemsSomnath Banerjee, Tushar Gupta. 298-303 [doi]
• SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon ValidationXinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Swarup Bhunia. 304-309 [doi]
• Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense AmplifierOghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov. 310-315 [doi]
• Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design OptimizationOleg Garitselov, Saraju P. Mohanty, Elias Kougianos. 316-321 [doi]
• Circuit Optimization at 22nm Technology NodeAngada B. Sachid, P. Paliwal, S. Joshi, M. Shojaei, D. Sharma, V. Ramgopal Rao. 322-327 [doi]
• Synthesis of Reversible Circuits Using Heuristic Search MethodKamalika Datta, Gaurav Rathi, Indranil Sengupta, Hafizur Rahaman. 328-333 [doi]
• Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic SynthesisSajib Kumar Mitra, Ahsan Raja Chowdhury. 334-339 [doi]
• Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and MemoryLei Wang, Somnath Paul, Swarup Bhunia. 340-345 [doi]
• Eliminating Performance Penalty of ScanOzgur Sinanoglu. 346-351 [doi]
• A Silicon Testing Strategy for Pulse-Width FailuresSrinivas Vooka, Khushboo Agarwal, Abhijeet Shrivastava, Pranav Murthy, Ramakrishnan Venkatraman. 352-357 [doi]
• At-speed Testing of Asynchronous Reset De-assertion FaultsArvind Jain, Maheedhar Jalasutram, Srinivas Vooka, Prasun Nair, Neeraj Pradhan. 358-363 [doi]
• A Library for Passive Online Verification of Analog and Mixed-Signal CircuitsDebjit Pal, Pallab Dasgupta, Siddhartha Mukhopadhyay. 364-369 [doi]
• A Fast Equation Free Iterative Approach to Analog Circuit SizingSupriyo Maji, Pradip Mandal. 370-375 [doi]
• Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design AccuracySamiran Dam, Pradip Mandal. 376-381 [doi]
• Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig InterpolationMatthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker. 382-387 [doi]
• Formal Verification of Galois Field Multipliers Using Computer Algebra TechniquesJinpeng Lv, Priyank Kalla. 388-393 [doi]
• A Novel SMT-Based Technique for LFSR ReseedingSarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram. 394-399 [doi]
• Two Graph Based Circuit Simulator for PDE-Electrical AnalogyYogesh Dilip Save, H. Narayanan, Sachin B. Patkar. 400-405 [doi]
• Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact ModelTarun Kumar Agarwal, M. Jagadesh Kumar. 406-411 [doi]
• Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAMH. C. Srinivasaiah. 412-417 [doi]
• Customizing Instruction Set Extensible Reconfigurable Processors Using GPUsUnmesh D. Bordoloi, Bharath Suri, Swaroop Nunna, Samarjit Chakraborty, Petru Eles, Zebo Peng. 418-423 [doi]
• Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory BlocksAnandaroop Ghosh, Somnath Paul, Swarup Bhunia. 424-429 [doi]
• Intra-Task Dynamic Cache ReconfigurationHadi Hajimiri, Prabhat Mishra. 430-435 [doi]
• A Diagnosability Metric for Test Set Selection Targeting Better Fault DetectionSubhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur. 436-441 [doi]
• Test Planning for Core-based 3D Stacked ICs with Through-Silicon ViasBreeta SenGupta, Urban Ingelsson, Erik Larsson. 442-447 [doi]
• Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test ClockPriyadharshini Shanmugasundaram, Vishwani D. Agrawal. 448-453 [doi]