Table of Contents

• LightningSim: Fast and Accurate Trace-Based Simulation for High-Level SynthesisRishov Sarkar, Cong Hao. 1-11 [doi]
• PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAsMoazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang. 12-22 [doi]
• SCCL: An open-source SystemC to RTL translatorZhuanhao Wu, Maya B. Gokhale, Scott Lloyd, Hiren D. Patel. 23-33 [doi]
• Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAsXiaochen Hao, Mingzhe Zhang, Ce Sun, Zhuofu Tao, Hongbo Rong, Yu Zhang, Lei He, Eric Petit, Wenguang Chen, Yun Liang 0001. 34-40 [doi]
• Placement Optimization for NoC-Enhanced FPGAsSrivatsan Srinivasan, Andrew Boutros, Fatemehsadat Mahmoudi, Vaughn Betz. 41-51 [doi]
• BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAsYuzong Chen, Mohamed S. Abdelfattah. 52-62 [doi]
• A Machine Learning Approach for Predicting the Difficulty of FPGA Routing ProblemsAndrew David Gunter, Steven J. E. Wilton. 63-74 [doi]
• CXL over Ethernet: A Novel FPGA-based Memory Disaggregation Design in Data CentersChenjiu Wang, Ke He, Ruiqi Fan, Xiaonan Wang, Wei Wang, Qinfen Hao. 75-82 [doi]
• Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric ProgrammingYuhao Ding, Jiajun Wu 0007, Yizhao Gao, Maolin Wang, Hayden Kwok-Hay So. 83-93 [doi]
• MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous ResourcesJiajun Wu 0007, Jiajun Zhou, Yizhao Gao, Yuhao Ding, Ngai Wong, Hayden Kwok-Hay So. 94-104 [doi]
• Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity MeasuresAlireza Khataei, Gaurav Singh, Kia Bazargan. 105-113 [doi]
• Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA PlatformPengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie. 114-120 [doi]
• ATHEENA: A Toolflow for Hardware Early-Exit Network AutomationBenjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides. 121-132 [doi]
• Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAsAbhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde. 133-143 [doi]
• HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA DevicesPetros Toupas, Alexander Montgomerie-Corcoran, Christos-Savvas Bouganis, Dimitrios Tzovaras. 144-154 [doi]
• Power2Picture: Using Generative CNNs for Input Recovery of Neural Network Accelerators through Power Side-Channels on FPGAsLukas Huegle, Martin Gotthard, Vincent Meyers, Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori. 155-161 [doi]
• Computing and Compressing Electron Repulsion Integrals on FPGAsXin Wu, Tobias Kenter, Robert Schade, Thomas D. Kühne, Christian Plessl. 162-173 [doi]
• Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic TransformYuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang 0012. 174-183 [doi]
• SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA PlatformsAlec Lu, Zhenman Fang. 184-194 [doi]
• DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network InferenceHanqiu Chen, Cong Hao. 195-201 [doi]
• Designing a configurable IEEE-compliant FPU that supports variable precision for soft processorsChris Keilbart, YuHui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon. 202 [doi]
• HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural NetworksGeng Yang, Jie Lei 0001, Zhenman Fang, Yunsong Li, Jiaqing Zhang, Weiying Xie. 203 [doi]
• Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAsFumiya Kono, Naohito Nakasato, Maho Nakata. 204 [doi]
• Efficient Implementation of a Genetic Algorithm for the Capacitated Vehicle Routing Problem on a High-Performance FPGAMaximilian Jakob Heer, José Quevedo, Marwan F. Abdelatti, Resit Sendag, Manbir Sodhi. 205 [doi]
• An Efficient Piecewise Linear Approximation of Non-linear Operations for Transformer InferenceHaodong Lu 0001, Qichang Mei, Kun Wang 0005. 206 [doi]
• Feature Extraction Accelerator for Streaming Time SeriesPrithviraj Yuvaraj, Amin Akalantar, Eamonn J. Keogh, Philip Brisk. 207 [doi]
• UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and OptimizationYuan Dai, Yunhui Qiu, Qilong Zhu, Jingyuan Li, Wenbo Yin, Lingli Wang. 208 [doi]
• -1 Data Acquisition System for 6G PrototypingChristian Maximilian Karle, Marc Neu, Johannes Pfau, Jan Sperling, Jürgen Becker 0001. 209 [doi]
• FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning ApplicationsZainab Aizaz, Kavita Khare, Aizaz Tirmizi. 210 [doi]
• SpCNA: An FPGA-based Accelerator for Point Cloud Convolutional Neural NetworksGong-Lang Zhou, Kaiyuan Guo, Xiang Chen, Kwok Wa Leung. 211 [doi]
• A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow ProcessingAnna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck. 212 [doi]
• Improving Performance of HPC Kernels on FPGAs Using High-Level Resource ManagementAntonio Filgueras, Miquel Vidal, Daniel Jiménez-González, Carlos Álvarez 0001, Xavier Martorell. 213 [doi]
• Accelerating Graph Analytics with oneAPI and Intel FPGAsJames Bickerstaff, Luke Kljucaric, Alan D. George. 214 [doi]
• Decision Forest Training Accelerator Based on Binary Feature DecompositionThiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura. 215 [doi]
• b8c: SpMV accelerator implementation leveraging high memory bandwidthJosé Oliver 0002, Carlos Álvarez 0001, Teresa Cervero, Xavier Martorell, John D. Davis, Eduard Ayguadé. 216 [doi]
• Scalable Quantum Error Correction for Surface Codes using FPGANamitha Liyanage, Yue Wu, Alexander Deters, Lin Zhong 0001. 217 [doi]
• MSBF-LSTM: Most-significant Bit-first LSTM Accelerators with Energy Efficiency OptimisationsSige Bian, He Li 0008, Chengcheng Wang, Changjun Song, Yongming Tang. 218 [doi]
• Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level SynthesisThijs Havinga, Xianjun Jiao, Wei Liu 0019, Ingrid Moerman. 219 [doi]
• Dynamically Scheduled Memory Operations in Static High-Level SynthesisRobert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede. 220 [doi]
• Transformer-OPU: An FPGA-based Overlay Processor for Transformer NetworksYueyin Bai, Hao Zhou, Keqing Zhao, Jianli Chen, Jun Yu, Kun Wang 0005. 221 [doi]
• Compiler-Assisted Kernel Selection for FPGA-based Near-Memory Computing PlatformsVeronia Iskandar, Mohamed A. Abd El ghany, Diana Goehringer. 222 [doi]
• Clustering Classification on FPGAs for Neuromorphic Feature ExtractionLuke Kljucaric, Alan D. George. 223 [doi]
• Making BRAMs Compute: Creating Scalable Computational Memory Fabric OverlaysMD Arafat Kabir, Joshua Hollis, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001. 224 [doi]
• OCMGen: Extended Design Space Exploration with Efficient FPGA Memory InferenceSanjay Gandham, Lingxiang Yin, Hao Zheng 0005, Mingjie Lin. 225 [doi]
• PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture DesignBingbing Peng, Shaoyang Sun, Yuan Dai, Jingyuan Li, Yunhui Qiu, Kaihang Wang, Wenbo Yin, Lingli Wang. 226 [doi]
• Moth: A Hardware Accelerator for Neural Radiance Field Inference on FPGAYuanfang Wang, Yu Li, Haoyang Zhang, Jun Yu, Kun Wang. 227 [doi]
• FCCM 2023 PhD Student Forum Compendium of Abstracts: Held on 9th May, 2023, at Los Angeles, USADebjit Pal. 228-229 [doi]
• Reformulating the FPGA Routability Prediction Problem with Machine LearningAndrew David Gunter, Steve Wilton. 230-232 [doi]
• Hardware/Software Co-design for Machine Learning AcceleratorsHanqiu Chen, Cong Hao. 233-235 [doi]
• From Acceleration to Accelerating Acceleration: Modernizing the Accelerator Landscape using High-Level SynthesisRishov Sarkar, Cong Hao. 236-238 [doi]
• Power Side-Channel Attacks and Defenses for Neural Network AcceleratorsVincent Meyers, Mehdi B. Tahoori. 239-241 [doi]
• Enabling Elastic Resource Management in Cloud FPGAs via A Multi-layer Collaborative ApproachWenbin Teng, Lei Gong, Chao Wang 0003, Xuehai Zhou. 242-244 [doi]
• A Framework for Graph Machine Learning on Heterogeneous ArchitectureYi-Chien Lin, Viktor K. Prasanna. 245-246 [doi]
• DataMaster: A GNN-based Data Type Optimizer for Dataflow Design in FPGAZheyuan Zou, Lei Gong, Chao Wang 0003, Xuehai Zhou. 247-249 [doi]