Chirag Ravishankar - researchr alias

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Viewing Publication 1 - 14 from 14

2023

2019

TM ArchitectureBrian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer. fpga 2019: 84-93 [doi]

2018

Placement Strategies for 2.5D FPGA Fabric ArchitecturesChirag Ravishankar, Dinesh Gaitonde, Trevor Bauer. fpl 2018: 16-20 [doi]

SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAsChirag Ravishankar, Henri Fraisse, Dinesh Gaitonde. fpt 2018: 118-125 [doi]

2012

EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only)Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings. fpga 2012: 266 [doi]

Raising FPGA Logic Density Through Synthesis-Inspired ArchitectureJason Helge Anderson, Qiang Wang, Chirag Ravishankar. tvlsi, 20(3):537-550, 2012. [doi]

Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platformsChirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings. isqed 2012: 617-624 [doi]

EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chipChirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings. fpl 2012: 41-48 [doi]

FPGA power reduction by guarded evaluation considering physical informationChirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson. vlsi 2012: 271-274 [doi]

FPGA Power Reduction by Guarded Evaluation Considering Logic ArchitectureChirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings. tcad, 31(9):1305-1318, 2012. [doi]

2011

Parallel FPGA technology mapping using multi-core architecturesAndrew A. Kennings, Chirag Ravishankar. ccece 2011: 274-279 [doi]

2010

FPGA power reduction by guarded evaluationJason Helge Anderson, Chirag Ravishankar. fpga 2010: 157-166 [doi]

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