Jason Helge Anderson, Chirag Ravishankar. FPGA power reduction by guarded evaluation. In Peter Y. K. Cheung, John Wawrzynek, editors, Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. pages 157-166, ACM, 2010. [doi]
Abstract is missing.