Table of Contents

• FPGA-2010 pre-conference workshop on open-source for FPGAShepard Siegel, Michael J. Wirthlin. 1 [doi]
• Intel nehalem processor core made FPGA synthesizableGraham Schelle, Jamison Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003. 3-12 [doi]
• FPGA prototyping of an amba-based windows-compatible SoCKan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong, Xu Cheng. 13-22 [doi]
• Predicting the performance of application-specific NoCs implemented on FPGAsJason Lee, Lesley Shannon. 23-32 [doi]
• Combining multicore and reconfigurable instruction set extensionsZhimin Chen, Richard Neil Pittman, Alessandro Forin. 33-36 [doi]
• Energy efficient sensor node implementationsJan R. Frigo, Eric Y. Raby, Sean M. Brennan, Christophe Wolinski, Charles Wagner, François Charot, Edward Rosten, Vinod Kulathumani. 37-40 [doi]
• Efficient multi-ported memories for FPGAsCharles Eric LaForest, J. Gregory Steffan. 41-50 [doi]
• Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocksShreesha Srinath, Katherine Compton. 51-58 [doi]
• Bit-level optimization for high-level synthesis and FPGA-based accelerationJiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong. 59-68 [doi]
• Designing hardware with dynamic memory abstractionJirí Simsa, Satnam Singh. 69-72 [doi]
• High-throughput bayesian computing machine with reconfigurable hardwareMingjie Lin, Ilia Lebedev, John Wawrzynek. 73-82 [doi]
• High throughput and large capacity pipelined dynamic search tree on FPGAYi-Hua E. Yang, Viktor K. Prasanna. 83-92 [doi]
• FPMR: MapReduce framework on FPGAYi Shan, Bo Wang, Jing Yan, Yu Wang 0002, Ning-Yi Xu, Huazhong Yang. 93-102 [doi]
• Acceleration of an analytical approach to collateralized debt obligation pricingDharmendra P. Gupta, Paul Chow. 103-106 [doi]
• A 3d-audio reconfigurable processorDimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev. 107-110 [doi]
• Accelerating Monte Carlo based SSTA using FPGAJason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan, Yi Zou. 111-114 [doi]
• Axel: a heterogeneous cluster with FPGAs and GPUsKuen Hung Tsoi, Wayne Luk. 115-124 [doi]
• Server-side coprocessor updating for mobile devices with FPGAsChen Huang, Frank Vahid. 125-134 [doi]
• Accurately evaluating application performance in simulated hybrid multi-tasking systemsKyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton. 135-144 [doi]
• Programming high performance signal processing systems in high level languagesKees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro. 145 [doi]
• Towards scalable placement for FPGAsHuimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu. 147-156 [doi]
• FPGA power reduction by guarded evaluationJason Helge Anderson, Chirag Ravishankar. 157-166 [doi]
• A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAsDoris Chen, Deshanand Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz. 167-176 [doi]
• Variation-aware placement for FPGAs with multi-cycle statistical timing analysisGregory Lucas, Chen Dong, Deming Chen. 177-180 [doi]
• Global delay optimization using structural choicesAlan Mishchenko, Robert K. Brayton, Stephen Jang. 181-184 [doi]
• Building a faster boolean matcher using bloom filterChun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong. 185-188 [doi]
• Haptic rendering of deformable objects using a multiple FPGA parallel computing architectureBehzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici. 189-198 [doi]
• A 1 cycle-per-byte XML parsing acceleratorZefu Dai, Nick Ni, Jianwen Zhu. 199-208 [doi]
• A modular NFA architecture for regular expression matchingHao Wang, Shi Pu, Gabriel Knezek, Jyh-Charn Liu. 209-218 [doi]
• Scalable network virtualization using FPGAsDeepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao, Russell Tessier. 219-228 [doi]
• Degradation in FPGAs: measurement and modellingEdward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung. 229-238 [doi]
• On-line sensing for healthier FPGA systemsKenneth M. Zick, John P. Hayes. 239-248 [doi]
• Voter insertion algorithms for FPGA designs using triple modular redundancyJonathan M. Johnson, Michael J. Wirthlin. 249-258 [doi]
• Maximizing area-constrained partial fault tolerance in reconfigurable logicDavid L. Foster, Darrin M. Hanna. 259-262 [doi]
• The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton. 263-272 [doi]
• Efficient FPGAs using nanoelectromechanical relaysChen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra. 273-282 [doi]
• A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only)Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu. 283 [doi]
• Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only)Marc-Andre Daigneault, Jean-Pierre David. 283 [doi]
• An architecture for graphics processing in an FPGA (abstract only)Marcus Dutton, David C. Keezer. 283 [doi]
• FPGA implementation of highly parallelized decoder logic for network coding (abstract only)Sunwoo Kim, Won W. Ro. 284 [doi]
• Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only)Kristian Stevens, Henry Chen, Terry Filiba, Peter McMahon, Yun S. Song. 284 [doi]
• FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only)Rahul Bhattachrya, Santosh Biswas, Siddhartha Mukhopadhyay. 284 [doi]
• LambdaRank acceleration for relevance ranking in web search engines (abstract only)Jing Yan, Ning-Yi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-hsiung Hsu. 285 [doi]
• Memory efficient string matching: a modular approach on FPGAs (abstract only)Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna. 285 [doi]
• Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only)Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh. 285 [doi]
• A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only)Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell. 286 [doi]
• Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only)Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain. 286 [doi]
• A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only)Diana Goehringer, Michael Huebner, Michael Benz, Juergen Becker. 286 [doi]
• Multiplier architectures for FPGA double precision functions (abstract only)Y. Hamid, Martin Langhammer. 287 [doi]
• Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only)Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt. 287 [doi]
• Reconfigurable custom floating-point instructions (abstract only)Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin. 287 [doi]
• Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only)Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita. 288 [doi]
• Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only)Peter A. Jamieson, Keneth B. Kent. 288 [doi]
• LUT-based FPGA technology mapping for reliability (abstract only)Jason Cong, Kirill Minkovich. 288 [doi]
• A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only)Taiga Takata, Yusuke Matsunaga. 289 [doi]
• DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only)Yangyang Pan, Tong Zhang. 290 [doi]
• Scalable architecture for programmable quantum gate array (abstract only)Mingjie Lin, Yaling Ma. 290 [doi]
• Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only)Husain Parvez, Zied Marrakchi, Habib Mehrez. 290 [doi]
• Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only)Julien Lamoureux, Scott Miller, Mihai Sima. 290 [doi]
• Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only)Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris. 291 [doi]
• Modeling and simulation of nano quantum FPGAs (abstract only)Mohammed Niamat, Sowmya Panuganti, Tejas Raviraj. 291 [doi]
• High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only)Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita. 291 [doi]
• Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only)Shaoshan Liu, Richard Neil Pittman, Alessandro Forin. 292 [doi]
• Design and evaluation of a parameterizable NoC router for FPGAs (abstract only)Mike Brugge, Mohammed A. S. Khalid. 292 [doi]
• Energy reduction with run-time partial reconfiguration (abstract only)Shaoshan Liu, Richard Neil Pittman, Alessandro Forin. 292 [doi]
• FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only)Donglai Dai, Aniruddha Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi. 293 [doi]