A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only)

Taiga Takata, Yusuke Matsunaga. A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). In Peter Y. K. Cheung, John Wawrzynek, editors, Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. pages 289, ACM, 2010. [doi]

Abstract

Abstract is missing.