Vinod Kathail - researchr alias

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Viewing Publication 1 - 23 from 23

2020

Xilinx Vitis Unified Software PlatformVinod Kathail. fpga 2020: 173-174 [doi]

2016

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array PlatformSagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig. micro, 36(2):48-62, 2016. [doi]

SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoCVinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo. fpga 2016: 4 [doi]

2015

UltraScale+ MPSoC and FPGA familiesVamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig. hotchips 2015: 1-37 [doi]

2010

Programming high performance signal processing systems in high level languagesKees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro. fpga 2010: 145 [doi]

2008

Architecture Exploration for Low Power DesignVinod Kathail, Tom Miller. vlsid 2008: 10-11 [doi]

2007

Tutorial T8A: Automated Application Engine Synthesis from C AlgorithmsVinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar. vlsid 2007: 12 [doi]

2002

PICO: Automatically Designing Custom ComputersVinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman. Computer, 35(9):39-47, 2002. [doi]

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware AcceleratorsRobert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman. vlsisp, 31(2):127-142, 2002. [doi]

2001

Compiling for EPIC architecturesVinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau. pieee, 89(11):1676-1693, 2001. [doi]

2000

High-Level Synthesis of Nonprogrammable Hardware AcceleratorsRobert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider. asap 2000: 113 [doi]

1999

1998

Meld Scheduling: A Technique for Relaxing Scheduling ConstraintsSantosh G. Abraham, Vinod Kathail, Brian L. Deitrich. ijpp, 26(4):349-381, 1998.

1997

Techniques for critical path reduction of scalar programsMichael S. Schlansker, Vinod Kathail. ijpp, 25(3):147-181, 1997. [doi]

1996

Meld Scheduling: Relaxing Scheduling Constraints Across Region BoundariesSantosh G. Abraham, Vinod Kathail, Brian L. Deitrich. euromicro 1996: 308-321 [doi]

Parallelization of Control Recurrences for ILP ProcessorsMichael S. Schlansker, Vinod Kathail, Sadun Anik. ijpp, 24(1):65-102, 1996.

1995

Critical path reduction for scalar programsMichael S. Schlansker, Vinod Kathail. euromicro 1995: 57-69 [doi]

1994

Height reduction of control recurrences for ILP processorsMichael S. Schlansker, Vinod Kathail, Sadun Anik. euromicro 1994: 40-51 [doi]

1993

Acceleration of First and Higher Order Recurrences on Processors with Instruction Level ParallelismMichael S. Schlansker, Vinod Kathail. lcpc 1994: 406-429

1990

Optimal interpreters for lambda-calculus based functional languagesVinod Kathail. PhD thesis, Massachusetts Institute of Technology, Cambridge, MA, USA, 1990. [doi]

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