Abstract is missing.
- OLAF'16: Second International Workshop on Overlay Architectures for FPGAsHayden Kwok-Hay So, John Wawrzynek. 1 [doi]
- HyperPipelining of High-Speed Interface LogicGregg Baeckler. 2 [doi]
- Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAsPankaj Shanker. 3 [doi]
- SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoCVinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo. 4 [doi]
- FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA CompilerTan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen. 5-14 [doi]
- Agile Co-Design for a Reconfigurable DatacenterShlomi Alkalay, Hari Angepat, Adrian M. Caulfield, Eric S. Chung, Oren Firestein, Michael Haselman, Stephen Heil, Kyle Holohan, Matt Humphrey, Tamás Juhász, Puneet Kaur, Sitaram Lanka, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Andrew Putnam, Raja Seera, Rimon Tadros, Jason Thong, Lisa Woods, Derek Chiou, Doug Burger. 15 [doi]
- Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural NetworksNaveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao. 16-25 [doi]
- Going Deeper with Embedded FPGA Platform for Convolutional Neural NetworkJiantao Qiu, Jie Wang, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang, Ningyi Xu, Sen Song, Yu Wang, Huazhong Yang. 26-35 [doi]
- Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine ClassifierBingzhe Li, M. Hassan Najafi, David J. Lilja. 36-41 [doi]
- A Platform-Oblivious Approach for Heterogeneous Computing: A Case Study with Monte Carlo-based Simulation for Medical ApplicationsShih-Hao Hung, Min-yu Tsai, Bo-Yi Huang, Chia-Heng Tu. 42-47 [doi]
- A Case for Work-stealing on FPGAs with OpenCL AtomicsNadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides. 48-53 [doi]
- Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic CoolingZhiyuan Yang, Ankur Srivastava. 54-63 [doi]
- Stratix™ 10 High Performance Routable Clock NetworksCarl Ebeling, Dana How, David Lewis, Herman Schmit. 64-73 [doi]
- Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock NetworkHenri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani. 74-79 [doi]
- FPRESSO: Enabling Express Transistor-Level Exploration of FPGA ArchitecturesGrace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne. 80-89 [doi]
- Towards PVT-Tolerant Glitch-Free Operation in FPGAsSafeen Huda, Jason Anderson. 90-99 [doi]
- Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay MeasurementTimothy A. Linscott, Benjamin Gojman, Raphael Rubin, André DeHon. 100-104 [doi]
- FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First SearchGuohao Dai, Yuze Chi, Yu Wang, Huazhong Yang. 105-110 [doi]
- GraphOps: A Dataflow Library for Graph Analytics AccelerationTayo Oguntebi, Kunle Olukotun. 111-117 [doi]
- High Performance Linkage Disequilibrium: FPGAs Hold the KeyNikolaos Alachiotis, Gabriel Weisz. 118-127 [doi]
- LMC: Automatic Resource-Aware Program-Optimized Memory PartitioningHsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer. 128-137 [doi]
- Efficient Memory Partitioning for Parallel Data Access via Data ReuseJincheng Su, Fan Yang, Xuan Zeng, Dian Zhou. 138-147 [doi]
- Intel Acquires Altera: How Will the World of FPGAs be Affected?Derek Chiou. 148 [doi]
- PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA SystemsTuan D. A. Nguyen, Akash Kumar. 149-158 [doi]
- The Stratix™ 10 Highly Pipelined FPGA ArchitectureDavid M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken. 159-168 [doi]
- Case for Design-Specific Machine Learning in Timing Closure of FPGA DesignsQue Yanghua, Chinnakkannu Adaikkala Raj, Harnhua Ng, Kirvy Teo, Nachiket Kapre. 169-172 [doi]
- Just In Time Assembly of AcceleratorsSen Ma, Zeyad Aklah, David Andrews. 173-178 [doi]
- CASK: Open-Source Custom Architectures for Sparse KernelsPaul Grigoras, Pavel Burovskiy, Wayne Luk. 179-184 [doi]
- GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA DatapathsNachiket Kapre, Deheng Ye. 185-194 [doi]
- Resolve: Generation of High-Performance Sorting Architectures from High-Level SynthesisJanarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner. 195-204 [doi]
- SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space ProcessingMichael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David Lee, Jeffrey Draper. 205-214 [doi]
- Optimal Circuits for Streamed Linear Permutations Using RAMFrançois Serre, Thomas Holenstein, Markus Püschel. 215-223 [doi]
- High Level Synthesis of Complex Applications: An H.264 Video DecoderXinheng Liu, Yao Chen, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen. 224-233 [doi]
- Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level SynthesisXitong Gao, John Wickerson, George A. Constantinides. 234-243 [doi]
- Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian EliminationDavid Boland. 244-253 [doi]
- FGPU: An SIMT-Architecture for FPGAsMuhammed Al Kadi, Benedikt Janßen, Michael Hübner. 254-263 [doi]
- A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA SystemsGabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe. 264-273 [doi]
- A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only)Ehsan Ghasemi, Paul Chow. 274 [doi]
- An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only)Daolu Zha, Xi Jin, Tian Xiang. 274 [doi]
- A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only)Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda. 274 [doi]
- Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only)Ze-ke Wang, Huiyan Cheah, Johns Paul, Bingsheng He, Wei Zhang. 274 [doi]
- ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only)Wenchao Qian, Christopher Babecki, Robert Karam, Swarup Bhunia. 275 [doi]
- Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only)Pingakshya Goswami, Dinesh Bhatia. 275 [doi]
- Increasing the Utility of Self-Calibration Methods in High-Precision Time Measurement Systems (Abstract Only)Matthias Hinkfoth, Ralf Salomon. 275 [doi]
- Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract Only)Li-ting, Harri Wijaya, Nachiket Kapre. 276 [doi]
- Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only)James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides. 276 [doi]
- Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only)Ronak Kogta, Suresh Purini, Ajit Mathew. 276 [doi]
- An Activity Aware Placement Approach For 3D FPGAs (Abstract Only)Girish Deshpande, Dinesh Bhatia. 277 [doi]
- an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only)Tianqi Wang, Bo Peng, Xi Jin. 277 [doi]
- A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only)Jie Lei, Yu-Ting Chen, Yunsong Li, Jason Cong. 277 [doi]
- An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar (Abstract Only)Sabrina Zereen, Sundeep Lal, Mohammed Khalid, Sazzadur Chowdhury. 278 [doi]
- Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only)Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow. 278 [doi]
- An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only)Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang. 278 [doi]
- Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only)Sebastien Bellon, Claudio Favi, Miroslaw Malek, Marco Macchetti, Francesco Regazzoni. 279 [doi]
- DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only)Jing Ye, Yu Hu, Xiaowei Li 0001. 279 [doi]
- Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only)Yu Bai, Mingjie Lin. 279 [doi]
- Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only)Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai. 280 [doi]
- A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only)Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 281 [doi]
- A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only)Stefan Visser, Harald Homulle, Edoardo Charbon. 281 [doi]
- ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only)Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou. 281 [doi]
- Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only)Cédric Marchand 0002, Lilian Bossuet, Abdelkarim Cherkaoui. 282 [doi]
- Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only)Aaron Landy, Greg Stitt. 282 [doi]
- FPGA Power Estimation Using Automatic Feature Selection (Abstract Only)Yunxuan Yu, Lei He. 282 [doi]
- Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric (Abstract Only)Mohammed Alawad, Mingjie Lin. 283 [doi]
- HGum: Messaging Framework for Hardware Accelerators (Abstact Only)Sizhuo Zhang, Hari Angepat, Derek Chiou. 283 [doi]
- Low-Swing Signaling for FPGA Power Reduction (Abstract Only)Sayeh Sharifymoghaddam, Ali Sheikholeslami. 283 [doi]
- t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only)Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan. 284 [doi]