Table of Contents

• Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled CircuitsLana Josipovic, Andrea Guerrieri, Paolo Ienne. 1-10 [doi]
• Invited Tutorial: FPGA Hardware Security for Datacenters and BeyondKaspar Matas, Tuan La, Nikola Grunchevski, Khoa Dang Pham, Dirk Koch. 11-20 [doi]
• Establishing Trust in MicroelectronicsLee W. Lerner. 21 [doi]
• Thermal and Voltage Side and Covert Channels and Attacks in Cloud FPGAsJakub Szefer. 22 [doi]
• Multi-tenant FPGA Security: Challenges and OpportunitiesPatrick Koeberl. 23 [doi]
• FPGA / SoC Security: Arms Race in the CloudSteven McNeil. 24-25 [doi]
• What To Do With Datacenter FPGAs Besides Deep LearningAndrew Putnam. 26 [doi]
• Symbiosis in Action: Reconfigurable Architectures and EDAMahesh A. Iyer. 27-28 [doi]
• Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant EnvironmentTuan D. A. Nguyen, Akash Kumar 0001. 29-39 [doi]
• AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICsPengfei Xu 0011, Xiaofan Zhang, Cong Hao, Yang Zhao, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin. 40-50 [doi]
• HeteroHalide: From Image Processing DSL to Efficient FPGA AccelerationJiajie Li, Yuze Chi, Jason Cong. 51-57 [doi]
• Fingerprinting Cloud FPGA InfrastructuresShanquan Tian, Wenjie Xiong 0001, Ilias Giechaskiel, Kasper Rasmussen, Jakub Szefer. 58-64 [doi]
• Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial OptimizationYu Zou, Mingjie Lin. 65-75 [doi]
• High-Performance FPGA Network Switch ArchitecturePhilippos Papaphilippou, Jiuxi Meng, Wayne Luk. 76-85 [doi]
• Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment SimulatorTanner Young-Schultz, Lothar Lilge, Stephen Brown, Vaughn Betz. 86-96 [doi]
• Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm-Architecture Co-DesignQiuyue Sun, Amir Taherin, Yawo Siatitse, Yuhao Zhu 0001. 97-103 [doi]
• Real-Time Spatial 3D Audio Synthesis on FPGAs for Blind SailingAnish Singhani, Alexander Morrow. 104-110 [doi]
• When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural NetworkVladimir Rybalkin, Norbert Wehn. 111-121 [doi]
• Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural NetworksYunxuan Yu, Tiandong Zhao, Kun Wang, Lei He. 122-132 [doi]
• End-to-End Optimization of Deep Learning ApplicationsAtefeh Sohrabizadeh, Jie Wang, Jason Cong. 133-139 [doi]
• Architectural Enhancements in Intel® Agilex™ FPGAsJeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov. 140-149 [doi]
• Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable RoutingStefan Nikolic, Grace Zgheib, Paolo Ienne. 150-160 [doi]
• LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree ImplementationsSeyedRamin Rasoulinezhad, Siddhartha 0003, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong. 161-171 [doi]
• FPGAs will Never be the Same Again: How the Newest FPGA Architectures are Totally Disrupting the Entire FPGA Ecosystem as We Know ItRaymond X. Nijssen. 172 [doi]
• Xilinx Vitis Unified Software PlatformVinod Kathail. 173-174 [doi]
• StateMover: Combining Simulation and Hardware Execution for Efficient FPGA DebuggingSameh Attia, Vaughn Betz. 175-185 [doi]
• Buffer Placement and Sizing for High-Performance Dataflow CircuitsLana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella. 186-196 [doi]
• Closing Leaks: Routing Against Crosstalk Side-Channel AttacksZeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic. 197-203 [doi]
• Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAsOgnjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic. 204-210 [doi]
• Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAsThiem Van Chu, Kenji Kise, Kiyofumi Tanaka. 211-221 [doi]
• FPGA-Accelerated Samplesort for Large Data SetsHan Chen, Sergey Madaminov, Michael Ferdman, Peter Milder. 222-232 [doi]
• BiS-KM: Enabling Any-Precision K-Means on FPGAsZhenhao He, Zeke Wang, Gustavo Alonso. 233-243 [doi]
• Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level SynthesisJohannes de Fine Licht, Grzegorz Kwasniewski, Torsten Hoefler. 244-254 [doi]
• GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous PlatformsHanqing Zeng, Viktor K. Prasanna. 255-265 [doi]
• Reuse Kernels or Activations?: A Flexible Dataflow for Low-latency Spectral CNN AccelerationYue Niu, Rajgopal Kannan, Ajitesh Srivastava, Viktor K. Prasanna. 266-276 [doi]
• Finding and Understanding Bugs in FPGA Synthesis ToolsYann Herklotz, John Wickerson. 277-287 [doi]
• Combining Dynamic & Static Scheduling in High-level SynthesisJianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson. 288-298 [doi]
• Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAsJiantong Jiang, Zeke Wang, Xue Liu, Juan Gómez-Luna, Nan Guan, Qingxu Deng, Wei Zhang, Onur Mutlu. 299-309 [doi]
• Advanced Dataflow Programming using Actor Machines for High-Level SynthesisEndri Bezati, Mahyar Emami, James R. Larus. 310 [doi]
• Programming Abstractions for Configurable Hardware: Survey and Research DirectionsSamuel Dewan, Paulo Garcia. 310 [doi]
• Pipeline-aware Logic Deduplication in High-Level Synthesis for Post-Quantum Cryptography AlgorithmsChangsu Kim, Yongwoo Lee, Shinnung Jeong, Wen Wang 0007, Jakub Szefer, Hanjun Kim. 310 [doi]
• Unleashing the Power of FPGAs as Programmable SwitchesThomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois. 311 [doi]
• Productive Hardware Designs using Hybrid HLS-RTL DevelopmentBlaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim. 311 [doi]
• Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum FrequencyLicheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong. 311 [doi]
• Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-TreeParnian Mokri, Maziar Amiraskari, Yuelin Liu, Mark Hempstead. 312 [doi]
• Hardware Description Beyond Register-Transfer Level LanguagesOron Port, Yoav Etsion. 312 [doi]
• MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design FlowsPingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia. 312 [doi]
• ConvCloud: An Adaptive Convolutional Neural Network Accelerator on Cloud FPGAsYang Yang, Chao Wang, Lei Gong, Xuehai Zhou. 313 [doi]
• A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC FlowPrashanth Mohan, Oguz Atli, Onur O. Kibar, Ken Mai. 313 [doi]
• Scalable FPGA Median Filtering using Multiple Efficient PassesOscar Rahnama, Tommaso Cavallari, Philip H. S. Torr, Stuart Golodetz. 313 [doi]
• FeCaffe: FPGA-enabled Caffe with OpenCL for Deep Learning Training and Inference on Intel Stratix 10Ke He, Bo Liu, Yu Zhang, Andrew Ling, Dian Gu. 314 [doi]
• Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture SearchMohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane. 315 [doi]
• DOMIS: Dual-Bank Optimal Micro-Architecture for Iterative StencilsJuan Escobedo, Mingjie Lin. 315 [doi]
• Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic MeasurementJunzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang. 315 [doi]
• Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path InsertionAyan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar. 316 [doi]
• LPAC: A Low-Precision Accelerator for CNN on FPGAsTianyu Zhang, Tiantian Han, Lu Tian, Yi Li, Xijie Jia, Guangdong Liu, Pingbo An, Yingran Tan, Lingzhi Sui, Shaoxia Fang, Dongliang Xie, Michaela Blott, Yi Shan. 316 [doi]
• INCAME: INterruptible CNN Accelerator for Multi-robot ExplorationJincheng Yu, Zhilin Xu, Shulin Zeng, Chao Yu, Jiantao Qiu, Chaoyang Shen, Yuanfan Xu, Guohao Dai, Yu Wang, Huazhong Yang. 316 [doi]
• Enable Efficient and Flexible FPGA Virtualization for Deep Learning in the CloudShulin Zeng, Guohao Dai, Kai Zhong, Hanbo Sun, Guangjun Ge, Kaiyuan Guo, Yu Wang 0002, Huazhong Yang. 317 [doi]
• Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking ApproachMichaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle. 317 [doi]
• CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover SensorsSeyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic. 317 [doi]
• CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real TimeZhe Chen, Garrett Blair, Hugh T. Blair, Jason Cong. 318 [doi]
• Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCLAdel Ejjeh, Vikram Adve, Rob A. Rutenbar. 318 [doi]
• Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN AccelerationChen Wu, Mingyu Wang, Xinyuan Chu, Kun Wang, Lei He. 318 [doi]
• Maximizing CNN Throughput on FPGA ClustersRuihao Li, Ke Liu, Mengying Zhao, Zhaoyan Shen, Xiaojun Cai, Zhiping Jia. 319 [doi]
• Synthesis-Free, Flexible and Fast Hardware Library for Biophysically Plausible NeurosimulationsRene Miedema, Georgios Smaragdos, Mario Negrello, Zaid Al-Ars, Matthias Möller, Christos Strydis. 319 [doi]
• R2CNN: Recurrent Residual Convolutional Neural Network on FPGAHiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk. 319 [doi]
• HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAsMathew Hall, Vaughn Betz. 320 [doi]
• FTDL: An FPGA-tailored Architecture for Deep Learning SystemsRunbin Shi, Yuhao Ding, Xuechao Wei, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding. 320 [doi]
• Performance Evaluation and Power Analysis of Teraflop-scale Fluid Simulation with Stratix 10 FPGAAtsushi Koshiba, Kouki Watanabe, Takaaki Miyajima, Kentaro Sano. 321 [doi]
• On the Exploration of Connection-aware Partitioning for Parallel FPGA RoutingYun Zhou, Dries Vercruyce, Dirk Stroobandt. 321 [doi]
• Cash: A Single-Source Hardware-Software Codesign Framework for Rapid PrototypingBlaise Tine, Fares Elsabbagh, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim. 321 [doi]
• Cycle-Free FPGA Routing GraphsAng Li, David Wentzlaff. 322 [doi]
• High Density Pipelined 8bit Multiplier Systolic Arrays for FPGAMartin Langhammer, Sergey Gribok, Gregg Baeckler. 322 [doi]
• Reactive Signal Obfuscation with Time-Fracturing to Counter Information Leakage in FPGAsStephen M. Williams, Mingjie Lin. 322 [doi]
• An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational LoopsRupesh S. Shelar. 323 [doi]
• QTAccel: A Generic FPGA based Design for Q-Table based Reinforcement Learning AcceleratorsRachit Rajat, Yuan Meng, Sanmukh R. Kuppannagari, Ajitesh Srivastava, Viktor K. Prasanna, Rajgopal Kannan. 323 [doi]
• The Case for Hard Matrix Multiplier Blocks in an FPGAAman Arora, Zhigang Wei, Lizy John. 323 [doi]
• Accuracy-Aware Memory Allocation to Mitigate BRAM Errors for Voltage Underscaling on FPGA Overlay AcceleratorsTanvir Ahmed, Johannes Maximilian Kühn. 324 [doi]
• Performance Portable FPGA DesignNils Voss, Tobias Becker, Simon Tilbury, Georgi Gaydadjiev, Oskar Mencer, Anna Maria Nestorov, Enrico Reggiani, Wayne Luk. 324 [doi]
• Near-memory Acceleration for Scalable Phylogenetic InferenceNikolaos Alachiotis, Panagiotis Skrimponis, Emmanouil Pissadakis, Sundeep Rangan, Dionisios N. Pnevmatikatos. 324 [doi]
• FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGAYufan Zhang, Zhengjie Li, Jian Wang, Jinmei Lai. 325 [doi]
• INTB: A New FPGA Interconnect Model for Architecture ExplorationChengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai. 325 [doi]
• V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based PruningTaesu Kim, Daehyun Ahn, Jae-Joon Kim. 326 [doi]
• DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCsUnai Martinez-Corral, Guillermo Callaghan, Konstantinos Iordanou, Cosmin Gorgovan, Koldo Basterretxea, Mikel Luján. 326 [doi]