Mahesh A. Iyer - researchr alias

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Viewing Publication 1 - 27 from 27

2023

DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAsRachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan. ispd 2023: 175-184 [doi]

2022

DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning ToolkitRachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan. aspdac 2022: 300-306 [doi]

2020

2019

2017

An Effective Timing-Driven Detailed Placement Algorithm for FPGAsShounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan. ispd 2017: 151-157 [doi]

CAD Opportunities with Hyper-PipeliningMahesh A. Iyer. ispd 2017: 149 [doi]

LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAsLove Singhal, Mahesh A. Iyer, Saurabh N. Adya. dac 2017: [doi]

2016

Detailed placement for modern FPGAs using 2D dynamic programmingShounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan. iccad 2016: 9 [doi]

2009

On improving optimization effectiveness in interconnect-driven physical synthesisPrashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer. ispd 2009: 51-58 [doi]

2003

A Robust and Scalable Technique for the Constraints Solving Problem in High-Level VerificationMahesh A. Iyer. mtv 2003: 95 [doi]

Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random SimulationMahesh A. Iyer. itc 2003: 299-308 [doi]

2000

FILL and FUNI: algorithms to identify illegal states and sequentially untestable faultsDavid E. Long, Mahesh A. Iyer, Miron Abramovici. todaes, 5(3):631-657, 2000. [doi]

1999

High Time For High Level ATPGMahesh A. Iyer. itc 1999: 1112

A Robust Solution to the Timing Convergence Problem in High-Performance DesignNarendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking. iccd 1999: 250-257 [doi]

Wavefront Technology MappingLeon Stok, Andrew J. Sullivan, Mahesh A. Iyer. date 1999: 531 [doi]

1996

FIRE: a fault-independent combinational redundancy identification algorithmMahesh A. Iyer, Miron Abramovici. tvlsi, 4(2):295-301, 1996. [doi]

Identifying Sequential Redundancies Without SearchMahesh A. Iyer, David E. Long, Miron Abramovici. dac 1996: 457-462 [doi]

Surprises in Sequential Redundancy IdentificationMahesh A. Iyer, David E. Long, Miron Abramovici. date 1996: 88-95 [doi]

1995

Energy models for delay testingSrimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal. tcad, 14(6):728-739, 1995. [doi]

Identifying sequentially untestable faults using illegal statesDavid E. Long, Mahesh A. Iyer, Miron Abramovici. vts 1995: 4-11 [doi]

1994

Low-Cost Redundancy Identification for Combinatorial CircuitsMahesh A. Iyer, Miron Abramovici. vlsid 1994: 315-318

Sequentially Untestable Faults Identified Without Search ( Simple Implications Beat Exhaustive Search! )Mahesh A. Iyer, Miron Abramovici. itc 1994: 259-266

1992

One-Pass Redundancy Identification and RemovalMiron Abramovici, Mahesh A. Iyer. itc 1992: 807-815

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