Abstract is missing.
- Technology Options for Beyond-CMOSIan Young. 1 [doi]
- The Quest for The Ultimate Learning MachinePradeep Dubey. 3 [doi]
- Deep Learning in the Enhanced CloudEric Chung. 5 [doi]
- Bilinear Lithography Hotspot DetectionHang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu. 7-14 [doi]
- Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine LearningWei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena. 15-21 [doi]
- Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable PlatformIvo Bolsens. 23 [doi]
- How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design libraryTiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla, José Luís Güntzel. 25-31 [doi]
- Rsyn: An Extensible Physical Synthesis FrameworkGuilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis. 33-40 [doi]
- Research Challenges in Security-Aware Physical DesignRamesh Karri. 41 [doi]
- Challenges and Opportunities: From Near-memory Computing to In-memory ComputingSoroosh Khoram, Yue Zha, Jialiang Zhang, Jing Li. 43-46 [doi]
- Physical Design Considerations of One-level RRAM-based Routing MultiplexersXifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon. 47-54 [doi]
- Hierarchical and Analytical Placement Techniques for High-Performance Analog CircuitsBiying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan. 55-62 [doi]
- Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling TrendLee-Chung Lu. 63 [doi]
- Modern Challenges in Constructing ClocksCharles J. Alpert. 65 [doi]
- Clock Tree Construction based on Arrival Time ConstraintsRickard Ewetz, Cheng-Kok Koh. 67-74 [doi]
- A Fast Incremental Cycle Ratio AlgorithmGang Wu, Chris Chu. 75-82 [doi]
- iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing AnalysisPei-Yu Lee, Iris Hui-Ru Jiang, Ting-You Yang. 83-89 [doi]
- DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning AssignmentJiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan. 91-98 [doi]
- Automatic Cell Layout in the 7nm EraPascal Cremer, Stefan Hougardy, Jan Schneider, Jannik Silvanus. 99-106 [doi]
- Improving Detailed Routability and Pin Access with 3D Monolithic Standard CellsDaohang Shi, Azadeh Davoodi. 107-112 [doi]
- The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his ApprenticesYuichi Nakamura. 113-114 [doi]
- Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit PlacementYao-Wen Chang. 115-120 [doi]
- 100x Evolution of Video Codec ChipsJinjia Zhou, Dajiang Zhou, Satoshi Goto. 121-122 [doi]
- Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and BeyondIlgweon Kang, Chung-Kuan Cheng. 123-128 [doi]
- Past, Present and Future of the ResearchSatoshi Goto. 129-130 [doi]
- Interesting Problems in Physical SynthesisPei-Hsin Ho. 131 [doi]
- Pin Accessibility-Driven Detailed Placement RefinementYixiao Ding, Chris Chu, Wai-Kei Mak. 133-140 [doi]
- A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum MovementNima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Laleh Behjat. 141-148 [doi]
- CAD Opportunities with Hyper-PipeliningMahesh A. Iyer. 149 [doi]
- An Effective Timing-Driven Detailed Placement Algorithm for FPGAsShounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan. 151-157 [doi]
- Clock-Aware FPGA Placement ContestStephen Yang, Chandra Mulpuri, Sainath Reddy, Meghraj Kalase, Srinivasan Dasasathyan, Mehrdad E. Dehkordi, Marvin Tom, Rajat Aggarwal. 159-164 [doi]