Table of Contents

• Becoming More Tolerant: Designing FPGAs for Variable Supply VoltageIbrahim Ahmed 0001, Linda L. Shen, Vaughn Betz. 1-8 [doi]
• Bent Routing Pattern for FPGAXibo Sun, Hao Zhou, Lingli Wang. 9-16 [doi]
• Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy EfficiencyMark Wijtvliet, Jos Huisken, Luc Waeijen, Henk Corporaal. 17-23 [doi]
• Timing-Aware Routing in the RapidWright FrameworkLeo Liu, Nachiket Kapre. 24-30 [doi]
• Finding a Needle in the Haystack of Hardened Interconnect PatternsStefan Nikolic, Grace Zgheib, Paolo Ienne. 31-37 [doi]
• Analysis of Performance Variation in 16nm FinFET FPGA DevicesKonstantinos Maragos, Endri Taka, George Lentaris, Ioannis Stratakos, Dimitrios Soudris. 38-44 [doi]
• Measuring Long Wire Leakage with Ring Oscillators in Cloud FPGAsIlias Giechaskiel, Kasper Bonne Rasmussen, Jakub Szefer. 45-50 [doi]
• Runtime-Programmable Pipelines for Model Checkers on FPGAsMrunal Patel, Shenghsun Cho, Michael Ferdman, Peter Milder. 51-58 [doi]
• FPGA-Based Simulated Bifurcation MachineKosuke Tatsumura, Alexander Dixon, Hayato Goto. 59-66 [doi]
• On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAsXinyu Chen, Ronak Bajaj, Yao Chen, Jiong He, Bingsheng He, Weng-Fai Wong, Deming Chen. 67-73 [doi]
• Dataflow Acceleration of Smith-Waterman with Traceback for High Throughput Next Generation SequencingKonstantina Koliogeorgi, Nils Voss, Sotiria Fytraki, Sotirios Xydis, Georgi Gaydadjiev, Dimitrios Soudris. 74-80 [doi]
• Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision RegimesQiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung. 81-87 [doi]
• Accelerating Physics Engine Components with Embedded FPGAsPetros Toupas, Andreas Brokalakis, Ioannis Papaefstathiou. 88-94 [doi]
• An FPGA-Based Architecture to Simulate Cellular Automata with Large Neighborhoods in Real TimeNikolaos Kyparissas, Apostolos Dollas. 95-99 [doi]
• Accelerating the Merge Phase of Sort-Merge JoinPhilippos Papaphilippou, Holger Pirk, Wayne Luk. 100-105 [doi]
• Evaluating the Hardware Cost of the Posit Number SystemYohann Uguen, Luc Forget, Florent de Dinechin. 106-113 [doi]
• Extracting INT8 Multipliers from INT18 MultipliersMartin Langhammer, Bogdan Pasca, Gregg Baeckler, Sergey Gribok. 114-120 [doi]
• Efficient Pattern Recognition Algorithm Including a Fast Retina Keypoint FPGA ImplementationLester Kalms, Maximilian Hajduk, Diana Göhringer. 121-128 [doi]
• Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision ApplicationsMarie Nguyen, Robert Tamburo, Srinivasa G. Narasimhan, James C. Hoe. 129-135 [doi]
• A High-Performance CNN Processor Based on FPGA for MobileNetsDi Wu 0013, Yu Zhang, Xijie Jia, Lu Tian, Tianping Li, Lingzhi Sui, Dongliang Xie, Yi Shan. 136-143 [doi]
• A Flexible Design Automation Tool for Accelerating Quantized Spectral CNNsRachit Rajat, Hanqing Zeng, Viktor K. Prasanna. 144-150 [doi]
• A Data-Center FPGA Acceleration Platform for Convolutional Neural NetworksXiaoyu Yu, Jianlin Gao, Yuwei Wang, Jie Miao, Ephrem Wu, Heng Zhang, Yu Meng, Bo Zhang, Biao Min, Dewei Chen. 151-158 [doi]
• Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs SamplingGlenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks 0001, Gu-Yeon Wei. 159-165 [doi]
• Automatic Compiler Based FPGA Accelerator for CNN TrainingShreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao 0001, Jae-sun Seo. 166-172 [doi]
• InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data ProcessingShengwen Liang, Ying Wang 0001, Cheng Liu, Huawei Li, Xiaowei Li 0001. 173-179 [doi]
• FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural NetworkHiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato. 180-186 [doi]
• Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAsShuanglong Liu, Wayne Luk. 187-193 [doi]
• Characterizing Power Distribution Attacks in Multi-User FPGA EnvironmentsGeorge Provelengios, Daniel Holcomb, Russell Tessier. 194-201 [doi]
• Physical Side-Channel Attacks and Covert Communication on FPGAs: A SurveySeyedeh Sharareh Mirzargar, Mirjana Stojilovic. 202-210 [doi]
• Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware PrimitivesRashmi Agrawal, Lake Bu, Alan Ehret, Michel A. Kinsy. 211-217 [doi]
• A Highly-Portable True Random Number Generator Based on Coherent SamplingAdriaan Peetermans, Vladimir Rozic, Ingrid Verbauwhede. 218-224 [doi]
• Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design MethodologiesFarnoud Farahmand, Duc Tri Nguyen, Viet B. Dang, Ahmed Ferozpuri, Kris Gaj. 225-231 [doi]
• Network Intrusion Detection Using Neural Networks on FPGA SoCsLenos Ioannou, Suhaib A. Fahmy. 232-238 [doi]
• Beyond the Limits: SHA-3 in Just 49 SlicesVictor Arribas. 239-245 [doi]
• FPGA Accelerated Deep Learning Radio Modulation Classification Using MATLAB System Objects & PYNQAndrew Maclellan, Lewis McLaughlin, Louise Crockett, Robert W. Stewart. 246-247 [doi]
• Spiking Row-by-Row FPGA Multi-Kernel and Multi-Layer Convolution ProcessorRicardo Tapiador-Morales, Antonio Rios-Navarro, Juan Pedro Dominguez-Morales, Daniel Gutierrez-Galan, Alejandro Linares-Barranco. 248-249 [doi]
• A Distributed Model of Computation for Reconfigurable Devices Based on a Streaming ArchitecturePaolo Cretaro. 250-251 [doi]
• Neural Network Overlay Using FPGA DSP BlocksLenos Ioannou, Suhaib A. Fahmy. 252-253 [doi]
• DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random AccessesMikhail Asiatici, Paolo Ienne. 254-262 [doi]
• NARMADA: Near-Memory Horizontal Diffusion Accelerator for Scalable Stencil ComputationsGagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Sander Stuijk, Henk Corporaal. 263-269 [doi]
• Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache ArrowJohan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, Peter Hofstee. 270-277 [doi]
• Data Stream Statistics Over Sliding Windows: How to Summarize 150 Million Updates Per Second on a Single NodeGrigorios Chrysos 0001, Odysseas Papapetrou, Dionisios N. Pnevmatikatos, Apostolos Dollas, Minos N. Garofalakis. 278-285 [doi]
• Limago: An FPGA-Based Open-Source 100 GbE TCP/IP StackMario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio López-Buedo. 286-292 [doi]
• System Architecture for Network-Attached FPGAs in the Cloud using Partial ReconfigurationBurkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey. 293-300 [doi]
• Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA DeviceSeungwon Min, Sitao Huang, Mohamed El-Hadedy, Jinjun Xiong, Deming Chen, Wen-mei Hwu. 301-306 [doi]
• High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream ProcessingRoberto Sierra, Filippo Mangani, Carlos Carreras, Gabriel Caffarena. 307-313 [doi]
• A Dynamic Memory Allocation Library for High-Level SynthesisNicholas V. Giamblanco, Jason H. Anderson. 314-320 [doi]
• A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU PlatformYuchen Ren, Zhijian Liao, Xiaozhong Shi, Jinyu Xie, Yunhui Qiu, Hankun Lv, Wenbo Yin, Lingli Wang, Bowei Yu, Hua Chen, Xianjun He. 321-325 [doi]
• Specializing FGPU for Persistent Deep LearningRui Ma, Derek Chiou, Jia-Ching Hsu, Tian Tan 0007, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu. 326-333 [doi]
• A Deep Learning Framework to Predict Routability for FPGA Circuit PlacementAbeer Alhyari, Ahmed Shamli, Ziad Abuwaimer, Shawki Areibi, Gary Gréwal. 334-341 [doi]
• Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning ProblemsAnanda Samajdar, Tushar Garg, Tushar Krishna, Nachiket Kapre. 342-349 [doi]
• Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGAMário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto. 350-353 [doi]
• Reducing Dynamic Power in Streaming CNN Hardware Accelerators by Exploiting Computational RedundanciesDuvindu Piyasena, Rukshan Wickramasinghe, Debdeep Paul, Siew Kei Lam, Meiqing Wu. 354-359 [doi]
• TensorFlow to Cloud FPGAs: Tradeoffs for Accelerating Deep Neural NetworksStefan Hadjis, Kunle Olukotun. 360-366 [doi]
• OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAsXifan Tang, Edouard Giacomin, Aurélien Alacchi, Baudouin Chauviere, Pierre-Emmanuel Gaillardon. 367-374 [doi]
• Tinsel: A Manythread Overlay for FPGA ClustersMatthew Naylor, Simon W. Moore, David B. Thomas. 375-383 [doi]
• Preallocating Resources for Distributed Memory Based FPGA DebugRobert Hale, Brad L. Hutchings. 384-390 [doi]
• Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAsHossein Omidian, Guy G. F. Lemieux. 391-396 [doi]
• Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis DesignHosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi, Sara Bondi, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Setareh Rafatirad. 397-403 [doi]
• FPGA Accelerated FPGA PlacementShounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan. 404-410 [doi]
• Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRATakuya Kojima, Naoki Ando, Yusuke Matsushita, Hideharu Amano. 411-412 [doi]
• An FPGA Implementation of Real-Time Object Detection with a Thermal CameraMasayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara. 413-414 [doi]
• Storing Parquet Tile by Tile: Application-Aware Storage with DeduplicationLucas Kuhring, Zsolt István. 415-416 [doi]
• Demonstration of Flow-in-Cloud: A Multi-FPGA SystemKazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, YuXi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano. 417-418 [doi]
• Demonstration of a Multimode SoC FPGA-Based Acoustic CameraBruno da Silva, Laurent Segers, An Braeken, Abdellah Touhafi. 419-420 [doi]
• Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNsYounmin Bae, Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Hyesoon Kim. 421 [doi]
• ZytleBot: FPGA Integrated Development Platform for ROS Based Autonomous Mobile RobotYasuhiro Nitta, Sou Tamura, Hideki Takase. 422-423 [doi]
• Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGAAkira Jinguji, Youki Sada, Hiroki Nakahara. 424-425 [doi]
• The CEDARtools Platform - Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access PatternsThomas Preußer, Alexander Weiss. 426-427 [doi]
• A Self-Calibrating True Random Number GeneratorAdriaan Peetermans, Milos Grujic, Vladimir Rozic, Ingrid Verbauwhede. 428 [doi]
• The FOS (FPGA Operating System) DemoAnuj Vaishnav, Khoa Dang Pham, Kristiyan Manev, Dirk Koch. 429 [doi]