José T. de Sousa - researchr alias

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Viewing Publication 1 - 40 from 40

2023

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product UnitsMário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto. trets, 16(1), March 2023. [doi]

2022

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGADavid Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias. staeors, 15:3600-3611, 2022. [doi]

2021

2020

2019

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA CoresLuís Fiolhais, Fernando Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa. iscas 2019: 1-5 [doi]

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGAMário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto. fpl 2019: 350-353 [doi]

2018

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAsMário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto. fpl 2018: 399-402 [doi]

2017

K-means clustering on CGRAJoão D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias. fpl 2017: 1-4 [doi]

Parallel dot-products for deep learning on FPGAMário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto. fpl 2017: 1-4 [doi]

2016

Versat, a Minimal Coarse-Grain Reconfigurable ArrayJoão D. Lopes, José T. de Sousa. vecpar 2017: 174-187 [doi]

2008

Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtractionRomanelli Lodron Zuim, José T. de Sousa, Claudionor N. Coelho. iet-cdt, 2(1):30-39, 2008. [doi]

2006

A Fast SAT Solver Strategy Based on Negated ClausesRomanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.. vlsi 2006: 110-115 [doi]

A fast SAT solver algorithm best suited to reconfigurable hardwareRomanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.. sbcci 2006: 131-136 [doi]

2005

Heuristic-Based Backtracking Relaxation for Propositional SatisfiabilityAteet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva. JAR, 35(1-3):3-24, 2005. [doi]

A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital CircuitsVictor Gonçalves, José T. de Sousa, Fernando M. Gonçalves. fpl 2005: 481-486

2004

Guest Editors Introduction: Field Programmable Logic and ApplicationsPeter Y. K. Cheung, George A. Constantinides, José T. de Sousa. TC, 53(11):1361-1362, 2004. [doi]

Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded ProcessorC. J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa. fpl 2004: 344-353 [doi]

2003

2002

DARP - A Digital Audio Reconfigurable ProcessorJosé T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura. fpl 2002: 556-566 [doi]

On Implementing a Configware/Software SAT SolverN. A. Reis, José T. de Sousa. fccm 2002: 282-283 [doi]

2001

A Configurable Hardware/Software Approach to SAT SolvingJosé T. de Sousa, João P. Marques Silva, Miron Abramovici. fccm 2001: 239-248 [doi]

2000

A SAT Solver Using Reconfigurable Hardware and Virtual LogicMiron Abramovici, José T. de Sousa. JAR, 24(1/2):5-36, 2000.

Reducing the Complexity of Defect Level Modeling Using the Clustering EffectJosé T. de Sousa, Vishwani D. Agrawal. date 2000: 640-644 [doi]

1999

A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable HardwareMiron Abramovici, José T. de Sousa, Daniel G. Saab. dac 1999: 684-690 [doi]

A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable HardwareMiron Abramovici, José T. de Sousa. fccm 1999: 306-307 [doi]

On Defect-Level Estimation and the Clustering EffectJosé T. de Sousa. ifip10-5 2000: 257-268

1997

Diagnosis of Boards for Realistic Interconnect ShortsJosé T. de Sousa, Peter Y. K. Cheung. et, 11(2):157-171, 1997. [doi]

Improved diagnosis of realistic interconnect shortsJosé T. de Sousa, Peter Y. K. Cheung. date 1997: 501-505 [doi]

1996

Defect level evaluation in an IC design environmentJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams. tcad, 15(10):1286-1293, 1996. [doi]

Realistic Fault Extraction for BoardsJosé T. de Sousa, T. Shen, Peter Y. K. Cheung. date 1996: 612 [doi]

1994

Fault Modeling and Defect Level Projections in Digital ICsJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams. eurodac 1994: 436-442

1992

Physical DFT for High Coverage of Realistic FaultsM. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. itc 1992: 642-651

1991

IC Defects-Based Testability AnalysisJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira. itc 1991: 500-509

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