Table of Contents

• Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer PlatformWim J. C. Melis, Peter Y. K. Cheung, Wayne Luk. 3-12 [doi]
• A Massively Parallel RC4 Key Search EngineKuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong. 13-21 [doi]
• An FPGA Implementation of Triangle Mesh DecompressionTulika Mitra, Tzi-cker Chiueh. 22 [doi]
• Single-Chip Gigabit Mixed-Version IP Router on Virtex-II ProGordon J. Brebner. 35-44 [doi]
• Control and Configuration Software for a Reconfigurable Networking Hardware PlatformTodd S. Sproull, John W. Lockwood, David E. Taylor. 45 [doi]
• Peer-to-Peer Hardware-Software Interfaces for Reconfigurable FabricsMihai Budiu, Mahim Mishra, Ashwin R. Bharambe, Seth Copen Goldstein. 57-66 [doi]
• PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAsOskar Mencer. 67-76 [doi]
• Coarse-Grain Pipelining on Multiple FPGA ArchitecturesHeidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz. 77 [doi]
• FPGA-Based Template Matching Using Distance TransformsStefan Hezel, Andreas Kugel, Reinhard Männer, Dariu Gavrila. 89-97 [doi]
• Reconfigurable Shape-Adaptive Template Matching ArchitecturesJörn Gause, Peter Y. K. Cheung, Wayne Luk. 98 [doi]
• Assisting Network Intrusion Detection with Reconfigurable HardwareBrad L. Hutchings, R. Franklin, D. Carver. 111-120 [doi]
• GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet ProcessingPeter Bellows, Jaroslav Flidr, Tom Lehman, Brian Schott, Keith D. Underwood. 121-130 [doi]
• Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable LogicGokhan Memik, Seda Ogrenci Memik, William H. Mangione-Smith. 131 [doi]
• Using On-Chip Configurable Logic to Reduce Embedded System Software EnergyGreg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid. 143-151 [doi]
• Queue Machines: Hardware Compilation in HardwareHerman Schmit, Benjamin A. Levine, Benjamin Ylvisaker. 152 [doi]
• Custom Computing Machines for the Set Covering ProblemChristian Plessl, Marco Platzner. 163-172 [doi]
• Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable ComputingBenjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan. 173-181 [doi]
• Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body SimulationsGerhard Lienhart, Andreas Kugel, Reinhard Männer. 182 [doi]
• Mobile Memory: Improving Memory Locality in Very Large Reconfigurable FabricsRong Yan, Seth Copen Goldstein. 195-204 [doi]
• Hardware-Assisted Fast RoutingAndré DeHon, Randy Huang, John Wawrzynek. 205 [doi]
• Optimum Wordlength AllocationGeorge A. Constantinides, Peter Y. K. Cheung, Wayne Luk. 219-228 [doi]
• Précis: A Design-Time Precision Analysis ToolMark L. Chang, Scott Hauck. 229-238 [doi]
• Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable SystemsDhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi. 239 [doi]
• Hyperspectral Image Compression on Reconfigurable PlatformsThomas W. Fry, Scott Hauck. 251-260 [doi]
• MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers. 261 [doi]
• On Sparse Matrix-Vector Multiplication with FPGA-Based SystemHossam A. ElGindy, Yen-Liang Shue. 273-274 [doi]
• Implementing a Simple Continuous Speech Recognition System on an FPGAStephen J. Melnikoff, Steven F. Quigley, Martin J. Russell. 275-276 [doi]
• RACER - A Rapid Prototyping Accelerator for Pulsed Neural NetworksCyprian Grassmann, Joachim K. Anlauf. 277-278 [doi]
• Accelerating Radiosity Calculations Using Reconfigurable PlatformsHenry Styles, Wayne Luk. 279-281 [doi]
• On Implementing a Configware/Software SAT SolverN. A. Reis, José T. de Sousa. 282-283 [doi]
• Reconfigurable Object Detection in FLIR Image SequencesJonathan E. Scalera, Creed F. Jones III, Maneesh Soni, Mark B. Bucciero, Peter M. Athanas, A. Lynn Abbott, Amitabh Mishra. 284-285 [doi]
• TCP-Stream Reassembly and State Tracking in HardwareMarc Necker, Didier Contis, David E. Schimmel. 286 [doi]
• Fast and Guaranteed C Compilation onto the PACT-XPP? Reconfigurable Computing PlatformJoão M. P. Cardoso, Markus Weinhardt. 291-292 [doi]
• Module Generators Driving the Compilation for Adaptive Computing SystemsAndreas Koch, Nico Kasprzyk. 293-294 [doi]
• System-Level Modelling and Implementation Technique for Run-Time Reconfigurable SystemsTero Rissa, Milan Vasilko, Jarkko Niittylahti. 295-296 [doi]
• Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software CodesignTheerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk. 297-298 [doi]
• Automatic Latency-Optimal Design of FPGA-Based Systolic ArraysJ. Greg Nash. 299-300 [doi]
• Compiling ATR Probing Codes for Execution on FPGA HardwareA. P. Wim Böhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar. 301-302 [doi]
• The Effects of Datapath Placement and C-Slow Retiming on Three Computational BenchmarksNicholas Weaver, John Wawrzynek. 303 [doi]
• A Scalable FPGA-Based Custom Computing Machine for a Medical Image ProcessingTakashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba. 307-308 [doi]
• The Design of the Amalgam Reconfigurable ClusterJoshua D. Walstrom, Jeffrey J. Cook, Derek B. Gottlieb, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter. 309-310 [doi]
• Mapping Algorithms to the Amalgam Programmable-Reconfigurable ProcessorJeffrey J. Cook, Derek B. Gottlieb, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter. 311 [doi]
• Customising Floating-Point DesignsAltaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi. 315-317 [doi]
• Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXesTim Courtney, Richard H. Turner, Roger Woods. 318 [doi]