Abstract is missing.
- Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA ApplicationShenggao Li, Yue Wu, Chunlei Shi, Mohammed Ismail. 1-10
- An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication DevicesG. B. Jackson, S. V. Awsare, L. D. Engh, M. A. Hemming, P. Holzmann, O. C. Kao, C. Mai-Liu, C. R. Palmer, A. Raina. 11-22
- A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS ProcessBingxin Li, Hannu Tenhunen. 23-34
- A Lower Power CMOS Micromixer for GHz Wireless ApplicationsYue Wu, Shenggao Li, Mohammed Ismail, Håkan Olsson. 35-46
- High Current, Low Voltage Current Mirrors and ApplicationsS. S. Rajput, S. S. Jamuar. 47-60
- Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC ApplicationsYue Wu, Hong-sun Kim, Fredrik Jonsson, Mohammed Ismail, Håkan Olsson. 61-68
- A Fast Parametric Model for Contact-Substrate CouplingNasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini. 69-76
- A Feature Associative Processor for Image Recognition Based on A-D merged ArchitectureAtsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie. 77-88
- Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia CommunicationsA. M. Rassau, G. Alagoda, David Lucas, J. Austin-Crowe, Kamran Eshraghian. 89-100
- Implementation of a Wavelet Transform Architecture for Image ProcessingCamille Diou, Lionel Torres, Michel Robert. 101-112
- Scalable Run Time Reconfigurable ArchitectureAbdellah Touhafi, Wouter Brissinck, Erik F. Dirkx. 113-124
- Frontier: A Fast Placement System for FPGAsRussell Tessier. 125-136
- Dynamically Reconfigurable Implementation of Control CircuitsNuno Lau, Valery Sklyarov. 137-148
- An IEEE Compliant Floating Point MAFR. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili. 149-160
- Design and Analysis of On-Chip CPU Pipelined CachesC. Ninos, Haridimos T. Vergos, Dimitris Nikolos. 161-172
- Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm ImplementationJoão M. S. Alcântara, Sergio C. Salomão, Edson do Prado Granja, Vladimir Castro Alves, Felipe M. G. França. 173-180
- Clock Distribution Strategy for IP-based DevelopmentRui L. Aguiar, Dinis M. Santos. 181-191
- An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory StructuresDavid H. Albonesi. 192-205
- Single Ended Pass-Transistor Logic - A Comparison with CMOS and CPLMihai Munteanu, Peter A. Ivey, N. Luke Seed, Marios Psilogeorgopoulos, Neil Powell, Istvan Bogdan. 206-218
- Multithreshold Voltage Technology for Low Power Bus ArchitectureAbdoul Rjoub, Odysseas G. Koufopavlou. 219-232
- Integrating Dynamic Power Management in the Design FlowAntônio Mota, Nuno Ferreira, Arlindo L. Oliveira, José C. Monteiro. 233-244
- Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSIStefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer. 245-256
- On Defect-Level Estimation and the Clustering EffectJosé T. de Sousa. 257-268
- FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC CircuitsJ. Soares Augusto, C. F. Beltrá Almeida. 269-280
- Design Error Diagnosis in Digital Circuits without Error ModelRaimund Ubar, Dominique Borrione. 281-292
- Efficient RLC Macromodels for Digital IC InterconnectBogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick. 293-304
- A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral SpecificationsAlex Doboli, Ranga Vemuri. 305-317
- A Linear Programming Approach for Synthesis of Mixed-Signal Interface ElementsAdrián Núñez-Aldana, Ranga Vemuri. 318-32
- RF Interface Design Using Mixed-Mode MethodologyAugusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne. 326-333
- History-Based Dynamic Minimization During BDD ConstructionRolf Drechsler, Wolfgang Günther. 334-345
- Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering ProblemsLuca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 346-361
- Satisfiability-Based Functional Delay Fault TestingJoonyoung Kim, João P. Marques Silva, Karem A. Sakallah. 362-372
- Verification of Abstracted Instruction Cache of TITAC2: A Case StudyTomohiro Yoneda. 373-384
- Speeding Up Look-up-Table Driven Logic SimulationRajeev Murgai, Fumiyasu Hirose, Masahiro Fujita. 385-397
- Efficient Verification of Behavioral Models Using Sequential Sampling TechniqueTom Chen, Isabelle Munn, Anneliese Amschler Andrews, Amjad Hajjar. 398-406
- Embedded Systems Design And Verification: Reuse Oriented Prototyping MethodologiesS. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres. 407-414
- A Virtual CMOS Library Approach for East Layout SynthesisFernando Moraes, Michel Robert, Daniel Auvergne. 415-426
- RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM RegimeAnanth Durbha, Srinivas Katkoori. 427-438
- Designing a Mask Programmable Matrix for Sequential CircuitsFernanda Lima, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D Avila, Luigi Carro, Ricardo Augusto da Luz Reis. 439-446
- Placements Benchmarks for 3-D VLSIStefan Thomas Obenaus, Ted H. Szymanski. 447-455
- Substrate Noise: Analysis, Models, and OptimizationEdoardo Charbon, Joel R. Phillips. 456-472
- Architectural Transformations for Hierarchical Algorithmic DescriptionsMarcio Yukio Teruya, Marius Strum, Wang Jiang Chau. 473-484
- An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUsJoão M. P. Cardoso, Horácio C. Neto. 485-496
- Object-Oriented Modeling and Co-Simulation of Embedded SystemsFlávio Rech Wagner, Márcio Oyamada, Luigi Carro, Márcio Eduardo Kreutz. 497-508
- Architectural Synthesis with Interconnection Cost ControlChristophe Jégo, Emmanuel Casseau, Eric Martin. 509-520
- CAE Environment for Electromechanical MicrosystemsR. Lerch, M. Kaltenbacher, H. Landes. 521-532
- Cost Consideration for Application Specific Microsystems Physical Design Stages - A New Approach for Microtechnological Process DesignRainer Brück, Andreas Priebe, Kai Hahn. 533-543
- Moving MEMS into Mainstream Applications: The MEMSCAP SolutionK. Liateni, D. Moulinier, B. Affour, A. Delpoux, Jean-Michel Karam. 544-556
- Trends in RF Simulation AlgorithmsJoel R. Phillips, Dan Feng. 557-568
- Device Modeling and Measurement for RF SystemsFranz Sischka. 569-582
- Reconfigurable Computing: Viable Applications and TrendsAlexandro M. S. Adário, Sergio Bampi. 583-594
- Hardware Synthesis from Term Rewriting SystemsJames C. Hoe, Arvind. 595-619
- A Synthesis Algorithm for Modular Design of Pipelined CircuitsMaria-Cristina V. Marinescu, Martin C. Rinard. 620-635
- A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMSB. F. Romanowicz, M. H. Zaman, S. F. Bart, V. L. Rabinovich, I. Tchertkov, C. Hsu, John R. Gilbert. 636-648
- SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters?Martin G. Walker, Keh-Jeng Chang, Christophe J. Bianchi. 649-658
- ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable InterconnectAndreas Kirschbaum, Jürgen Becker, Manfred Glesner. 659-670