Camille Diou - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 21 from 21

2021

Time-shift immunity for wireless sensor network based on discrete wavelet packetsChristophe Hüseyin Kizil, Camille Diou, Camel Tanougast. adt, 76(1):1-17, 2021. [doi]

2019

Genetic algorithms for scheduling in a CPU/FPGA architecture with heterogeneous communication delaysFadel Abdallah, Camel Tanougast, Imed Kacem, Camille Diou, Daniel Singer. candie, 137, 2019. [doi]

2017

A comparison of two metaheuristic algorithms for scheduling problem on a heterogeneous CPU/FPGA architecture with communication delaysFadel Abdallah, Camel Tanougast, Imed Kacem, Camille Diou, Daniel Singer. codit 2017: 294-299 [doi]

Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC ArchitectureHayat Daoud, Camel Tanougast, Mostefa Belarbi, Mikael Heil, Camille Diou. systems, 5(1):17, 2017. [doi]

2015

LOS/NLOS Identification Based on Stable Distribution Feature Extraction and SVM Classifier for UWB On-Body CommunicationsMohamed Tabaa, Camille Diou, Rachid Saadane, Abbas Dandache. juspn, 6(1):27-32, 2015. [doi]

2014

LOS/NLOS Identification based on Stable Distribution Feature Extraction and SVM Classifier for UWB On-body CommunicationsMohamed Tabaa, Camille Diou, Rachid Saadane, Abbas Dandache. ant 2014: 882-887 [doi]

A low-cost many-to-one WSN architecture based on UWB-IR and DWPTMohamed Tabaa, Camille Diou. codit 2014: 712-718 [doi]

2011

A Self-Checking Hardware Journal for a Fault-Tolerant Processor ArchitectureMohsin Amin, Abbas Ramazani, Fabrice Monteiro, Camille Diou, Abbas Dandache. ijrc, 2011, 2011. [doi]

2010

A Self-Checking HW Journal for a Fault Tolerant Processor ArchitectureMohsin Amin, Camille Diou, Fabrice Monteiro, Abbas Ramazani, Abbas Dandache. recosoc 2010: 67-71

Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for EducationCédric Killian, Camel Tanougast, M. Monteiro, Camille Diou, Abbas Dandache, S. Jovanovic. recosoc 2010: 135-139

2009

A HW/SW mixed mechanism to improve the dependability of a stack processorMohsin Amin, Fabrice Monteiro, Camille Diou, Abbas Ramazani, Abbas Dandache. icecsys 2009: 976-979 [doi]

A fault tolerant journalized stack processor architectureAbbas Ramazani, Mohsin Amin, Fabrice Monteiro, Camille Diou, Abbas Dandache. iolts 2009: 201-202 [doi]

2007

Stack processor architecture and development methods suitable for dependable applicationsMehdi Jallouli, Camille Diou, Fabrice Monteiro. recosoc 2007: 69-75

A cost-effective parallel architecture for the CodeRAKE receiverMazen Youssef, Fabrice Monteiro, Abbas Dandache, Camille Diou. icecsys 2007: 447-450 [doi]

2006

CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiverMazen Youssef, Camille Diou, Fabrice Monteiro, Abbas Dandache. icecsys 2006: 148-151 [doi]

2005

A multiprocessor architecture for fast packet processingAbbas Ramazani, Fabrice Monteiro, Camille Diou, Abbas Dandache. icecsys 2005: 1-4 [doi]

2002

Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP ApplicationsGilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy. date 2002: 553-558 [doi]

2001

An embedded core for the 2D wavelet transformCamille Diou, Lionel Torres, Michel Robert. etfa 2001: 179-186 [doi]

The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded SystemsGilles Sassatelli, Lionel Torres, Jérôme Galy, Gaston Cambon, Camille Diou. fpl 2001: 409-419 [doi]

2000

A Wavelet Core for Video ProcessingCamille Diou, Lionel Torres, Michel Robert. icip 2000: 395-398

1999

Implementation of a Wavelet Transform Architecture for Image ProcessingCamille Diou, Lionel Torres, Michel Robert. ifip10-5 2000: 101-112

Sign in or sign up to see more results.

runs on WebDSL