Table of Contents

• Distributed RLC Interconnect: Analytical Modelling Expressions for Crosstalk Noise EstimationH. J. Kadim, Lacina M. Coulibaly. 1-4 [doi]
• A New RF SiCMOS SDD Model for Quantifying Individual Contribution to Distortion from Transistor's Nonlinear ParametersAli Abuelmaatti, Iain Thayne. 5-8 [doi]
• Noise Modeling For Charge Amplification and SamplingPatrick Pittet, Guo-Neng Lu, Laurent Quiquerez. 9-12 [doi]
• General Model for the Deployment of Time-Delay Elements in Transistorized Electronic CircuitsLuis Nero Alves, Luis Barbosa, Rui L. Aguiar. 13-16 [doi]
• Multiconductor Transmission Lines Sensitivity via Two-Dimensional Laplace TransformLubomír Brancík. 17-20 [doi]
• Design and Analysis of A Class-E Frequency-Controlled Transcutaneous Energy Transfer SystemAhmad Mizannojehdehi, Maitham Shams, Tofy Mussivand. 21-24 [doi]
• Multiparameters monitoring for long term in-vivo characterization of electrode-tissues contactsGuillaume Lesbros, Mohamad Sawan. 25-28 [doi]
• An Efficient Micro-Stimulator Array Using Unitary-Size DAC With Adiabatic Baseband SchemeCihun-Siyong Alex Gong, Muh-Tian Shiue, Chun-Hsien Su, Yin Chang. 29-32 [doi]
• Design of Self-Sampling Based ASK Demodulator for Implantable MicrosystemCihun-Siyong Alex Gong, Chen-Lung Wu, Sheng-Yang Ho, Tong-Yi Chen, Jia-Chun Huang, Chia-Wei Su, Chun-Hsien Su, Yin Chang, Kuo-Hsing Cheng, Yu-lung Lo, Muh-Tian Shiue. 33-36 [doi]
• Comparison of Transconductance Reduction Techniques for the Design of a Very Large Time-Constant CMOS IntegratorIoannis Pachnis, Andreas Demosthenous, Nick Donaldson. 37-40 [doi]
• Continuous-time Sigma-Delta Modulators for Highly Digitised ReceiversLucien J. Breems, Robert H. M. van Veldhoven, Kathleen Philips, Robert Rutten, Gunnar Wetzker. 41-45 [doi]
• Quadrature Mismatch Shaping with a Complex, Data Directed SwapperStijn Reekmans, Benoit Catteau, Pieter Rombouts, Ludo Weyten. 46-49 [doi]
• Design of Cascaded Continuous-Time Sigma-Delta ModulatorsSusanna Patón, Manuel Sanchez-Renedo, Luis Hernández, Enrique Prefasi, Andreas Wiesbauer, Antonio Di Giandomenico, David San Segundo. 50-53 [doi]
• Use of the Step Invariant Transform to Design a 2nd Order Continuous Time Complex Sigma-Delta ADCNiall Duncan, Anthony Dunne, Michael Peter Kennedy. 54-57 [doi]
• Sigma-Delta Solutions for Future Wireless HandieldsAna Rusu, Mohammed Ismail. 58-61 [doi]
• Analysis of Wideband CMOS Low Noise Amplifiers using current-reuse configurationSaul Rodriguez Duenas, Li-Rong Zheng, Mohammed Ismail. 62-65 [doi]
• Concurrent Dual-Band Low Noise Amplifier for 802.11a/g WLAN applicationsOuail El-Gharniti, Eric Kerherve, Jean-Baptiste Begueret, Didier Belot. 66-69 [doi]
• Design and Implementation of BiFET LNAs for W-CDMA / IEEE 802.11a ApplicationsCristian Pavão Moreira, Eric Kerhervé, Pierre Jarry, Didier Belot. 70-73 [doi]
• Inversion-Coefficient Based Design of RF CMOS Low-Noise AmplifiersNikolaos Mavredakis, Matthias Bucher. 74-77 [doi]
• A Low-Voltage CMOS LNA Design Utilizing the Technique of Capacitive Feedback Matching NetworkChung-Yu Wu, Fadi Riad Shahroury. 78-81 [doi]
• Differential-Mode/Common-Mode Feedforward Transconductor for Low-Voltage Gm-C filtersPhanumas Khumsat, Apisak Worapishet, Klanarong Noulkaew, Theerachet Soorapanth. 82-85 [doi]
• A High-Linear Low-voltage CMOS Tunable Transconductor for VHF FilteringBelén Calvo, Santiago Celma, Maria Teresa Sanz, Jaime Ramírez-Angulo. 86-89 [doi]
• A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequencyAndrea Maniero, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani. 90-93 [doi]
• Automatic Tuning of Continuous Time Adaptive Bandpass FilterSaleh R. Al-Araji, Kahtan A. Mezher, Hassan Y. Al-Jasmi. 94-97 [doi]
• Oscillation-Based Test Structure and Method for OTA-C FiltersMasood ul-Hasan, Yichuang Sun. 98-101 [doi]
• An FFT Core for DVB-T/DVB-H ReceiversAinhoa Cortés, Juan Francisco Sevillano, Igone Vélez, Andoni Irizar. 102-105 [doi]
• An All-Digital Clock Frequency Caputring Circuitry For NRZ Data CommunicationsMuhammad E. S. Elrabaa. 106-109 [doi]
• A Methodology for Design Space Exploration in Embedded DSP ApplicationsGeorge Economakos, Kostas Anagnostopoulos, Isidoros Sideris. 110-113 [doi]
• Design and Implementation of a Correlation-based DSP Software for Narrowband Power Line Communication ReceiverHoussem Hajji, Adel Ghazel. 114-118 [doi]
• A Novel Merged Multiplier-Accumulator Embedded in DSP CoprocessorHadi Parandeh-Afshar, Mohsen Ahmadvand, Saeed Safari. 119-122 [doi]
• Delta-Sigma Modulators for Power-Efficient A/D Conversion in High-Speed Wireless CommunicationsAnas A. Hamoui, Franco Maloberti. 123-127 [doi]
• A Segmented Analog Calibration Scheme for Low-Power Multi-Bit Pipeline ADCsOlujide A. Adeniran, Andreas Demosthenous. 128-131 [doi]
• Power Optimization for Pipelined ADCs with Open-Loop Residue AmplifiersAthon Zanikopoulos, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund. 132-135 [doi]
• A 2nd Order 1-bit Complex Switched Capacitor Sigma-Delta ADC with 90dB SNDR in a 180kHz BandwidthAlan Bannon, Anthony Dunne, Daniel O'Hare, Matthew Miller, Omid Oliaei. 136-139 [doi]
• A 6b 100MS/s 0.28mm2 5mW 0.18um CMOS F/I ADC with a Novel Folder Reduction TechniqueJunho Moon, Seunghwi Jung, Sanghoon Hwang, Minkyu Song. 140-143 [doi]
• An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP SensorAnthony Kolar, Tarik Graba, Andréa Pinna, Olivier Romain, Bertrand Granado, Thomas Ea. 144-147 [doi]
• CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiverMazen Youssef, Camille Diou, Fabrice Monteiro, Abbas Dandache. 148-151 [doi]
• An experimental analysis of a new mixed grain-based dynamically reconfigurable architectureLuca Sterpone. 152-155 [doi]
• Rethinking Processor Design: Parameter CorrelationsNana B. Sam, Sally A. McKee, Prabhakar Kudva. 156-159 [doi]
• Supporting A Dynamic Program Signature: An Intrusion Detection Framework for MicroprocessorsKoji Inoue. 160-163 [doi]
• Power Modeling and Efficient FPGA Implementation of Color Space ConversionFaycal Bensaali, Abbes Amira, Shrutisagar Chandrasekaran. 164-167 [doi]
• An Efficient Bit-Detection and Timing Recovery Circuit for FPGAsPaolo Zicari, Pasquale Corsonello, Stefania Perri. 168-171 [doi]
• Design Space Exploration of Division over GF(2m) on FPGA: A Digit-Serial ApproachWilliam N. Chelton, Mohammed Benaissa. 172-175 [doi]
• FPGA Implementations of a Simplified Retinex Image Processing AlgorithmTommaso Balercia, Andrea Zitti, Henry Francesconi, Simone Orcioni, Massimo Conti. 176-179 [doi]
• High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAsLuciano Volcan Agostini, Sergio Bampi, Ivan Saraiva Silva. 180-183 [doi]
• Multi-Mode Wideband Voltage Controlled OscillatorsUlrich L. Rohde, Ajay K. Poddar. 184-187 [doi]
• High-Performance VCO for 5-GHz WLANs in 0.35 μm CMOS Standard TechnologyDomenico Zito, Domenico Pepe, Bruno Neri. 188-191 [doi]
• Design of a 1.2 V Low Phase Noise 1.6 GHz CMOS Buffered Quadrature Output VCO with Automatic Amplitude ControlOwen Casha, Ivan Grech, Joseph Micallef, Edward Gatt. 192-195 [doi]
• Analysis of Harmonic Distortion in the Colpitts OscillatorGaetano Palumbo, Melita Pennisi, Salvatore Pennisi. 196-199 [doi]
• A Design Approach for Low Phase Noise 5GHz Complementary Quadrature OscillatorYukio Hattori, Hiroki Sato, Akira Hyogo, Keitaro Sekine. 200-203 [doi]
• NMOS Low Drop-Out Regulator with Dynamic BiasingGianluca Giustolisi, Gaetano Palumbo, Christian Falconi, Arnaldo D'Amico. 204-207 [doi]
• Novel Approach to Low-Voltage Low-Power Bandgap Reference Voltage in Standard CMOS ProcessChristian Jesús B. Fayomi, Stephen J. Stratz. 208-211 [doi]
• Design of fuel-cell powered DC-DC converter for portable applications in digital CMOS technologyAndrea Boni, Alessandro Carboni, Alessio Facen. 212-215 [doi]
• High Linear Voltage References for on-chip CMOS Temperature SensorJoseph T.-s. Tsai, Herming Chiueh. 216-219 [doi]
• Low-Power Wordline Voltage Generator for Low-Voltage Flash MemoryTzu-Ming Wang, Ming-Dou Ker, Steve Yeh, Ya-Chun Chang. 220-223 [doi]
• Characterization of In-Phase/Quad-Phase Digital Downconversion Via Special Sampling SchemeJesse P. Somann, Yong C. Kim. 224-227 [doi]
• Multiple Input Digital Arbiter with Timestamp Assignment for Asynchronous Sensor ArraysMichael Hofstätter, Ahmed Nabil Belbachir, Ernst Bodenstorfer, Peter Schön. 228-231 [doi]
• Efficient Circuitry for Computing τ-adic Non-Adjacent FormKimmo Järvinen, Juha Forsten, Jorma Skyttä. 232-235 [doi]
• Time-Domain Synthesis of IIR Phase EqualizersMladen Vucic, Goran Molnar. 236-239 [doi]
• Spread Spectrum PWM Signal Generator for Fully Digital Audio AmplifierAkihiko Yoneya. 240-243 [doi]
• Explaining Hysteresis in Electronic Circuits: Robust Simulation and Design ExamplesAhmed S. Elwakil, Serdar Özoguz, R. Jada'a. 244-247 [doi]
• A Q-Enhanced Biquadratic Gm-C Filter for High Frequency ApplicationsMohsen Moezzi, Ramin Zanbaghi, Mojtaba Atarodi, Armin Tajalli. 248-251 [doi]
• Hazard Free Sawtooth Oscillator and Its Application in Ultra Low Current MonitoringLei Zhang 0033, Zhiping Yu, Xiangqing He. 252-255 [doi]
• A wide bandwidth voltage-follower with low distortion and high slew rateNikolaos Charalampidis, Khaled Hayatleh, Bryan L. Hart, F. John Lidgey. 256-259 [doi]
• A Novel CMOS Mini-LVDS Receiver for Flat-Plane ApplicationChung-Yuan Chen, Tai-Ping Sun. 260-263 [doi]
• Design Guidelines for Two-Stage Cascode-Compensated Operational AmplifiersHamed Aminzadeh, Reza Lotfi, Somayyeh Rahimian. 264-267 [doi]
• Simple Logic Threshold Conversion CircuitsCong-Kha Pham. 268-271 [doi]
• High Speed High Precision Voltage-Mode MAX and MIN CircuitsSarang Kazeminia, Abdollah Khoei, Kheirollah Hadidi. 272-275 [doi]
• A Sigma-Delta closed-loop digital microfluxgate magnetometerFabrice Gayral, Elisabeth Delevoye, Cyril Condemine, Éric Colinet, Fabien Mieyeville, Frédéric Gaffiot. 276-279 [doi]
• Fully Integrated Headphone DetectorDavid Guilherme, Nuno V. Caldeira, João Risques. 280-283 [doi]
• Periodically time-varying two-terminals at a steady state, description and identificationRadoslaw Klosinski. 284-287 [doi]
• Sub-1V Oguey's Current Reference Without ResistanceFabrice Guigues, Edith Kussener, Alexandre Malherbe, Benjamin Duval. 288-291 [doi]
• CMOS Realization of a Quantized-Output Classifier CircuitMerih Yildiz, Shahram Minaei, Izzet Cem Göknar. 292-295 [doi]
• Biobjective Hybrid Evolutionary Algorithm Applied to Resonator Filters of Arbitrary TopologyMaria José Pereira Dantas, Leonardo da C. Brito, Paulo Henrique Portela de Carvalho. 296-299 [doi]
• Transition from Sinusoidal to Relaxation Oscillations in Emitter-Coupled MultivibratorsIgor M. Filanovsky, Chris J. M. Verhoeven. 300-303 [doi]
• Wireless System for Temperature Measurement in Wheels, based on the ISM BandPaul Bustamante, Mikel Osinalde, Jon del Portillo, Gonzalo Solas. 304-309 [doi]
• Integrated instrumental chain for magnetic pulse measurement in strong static field environmentVincent Frick, Joris Pascal, Luc Hebrard, Jean-Philippe Blonde. 310-313 [doi]
• Global Shutter CMOS Image Sensor With Wide Dynamic RangeAlexander Belenky, Alexander Fish, Orly Yadid-Pecht. 314-317 [doi]
• The Performance Modeling of Ring Laser Gyro In Inertial NavigationShahram Mohammad Nejad, Maryam Pourmahyabadi. 318-321 [doi]
• Contributions to the analysis and design of an ADPLLCyril Joubert, Jean-François Bercher, Geneviève Baudoin. 322-325 [doi]
• Analysis and Design of Antireflection and Frequency Selective Surfaces with Stratified and inhomogeneous mediaMohsen Choubani, Fethi Choubani, Ali Gharsallah, Jacques David, N. E. Mastorakis. 326-330 [doi]
• Design of a SiGe Reconfigurable Power Amplifier for RF Applications: Device and Multi-standard ConsiderationsNathalie Deltimple, Eric Kerherve, Yann Deval, Didier Belot, Pierre Jarry. 331-334 [doi]
• Differential Cross-Coupled CMOS VCOs with Resistive and Inductive Tail BiasingSergio Gagliolo, Giacomo Pruzzo, Daniele D. Caviglia. 335-338 [doi]
• Low power CMOS transmitter for biomedical sensing devicesThierry Dupire, Louis-Francois Tanguay, Mohamad Sawan. 339-342 [doi]
• A novel compact dual-mode bandpass filter using fractal shaped resonatorsElias Hanna, Pierre Jarry, Eric Kerherve, Jean-Marie Pham. 343-346 [doi]
• Fuzzy logic based system for classification of atrial fibrillation cardiac arrhythmiasAli Messaoud, Mohamed Ben Messaoud, Abdennaceur Kachouri, Faiçal Sellami. 347-350 [doi]
• Design And Implementation Of A Monolithic Programme-Controlled System For Retinal ProsthesisCihun-Siyong Alex Gong, Muh-Tian Shiue, Yin Chang. 351-354 [doi]
• Reduction of color variability in color image segmentationH. Ben M'Hadheb, Ali Douik, M. M. Fendri, Mohamed Annabi. 355-358 [doi]
• High-Resolution 1H NMR Micro spectroscopy using an Implantable Micro-coilNicoleta Baxan, Adrian Rengle, André Briguet, Latifa Fakri-Bouchet, Jean-Francois Châteaux, Guillaume Pasquet, Pierre Morin. 359-362 [doi]
• An FPGA-based genetic microarray processing devicePedro Gómez Vilda, Francisco Díaz Pérez, Bogdan Belean, Raul Malutan, Benjamin Stetter, Rafael Martínez, Victoria Rodellar. 363-366 [doi]
• CMOS BDJ detector array with charge preamplifiers for sensitive biochemical analysisGenaro Carrillo, Guo-Neng Lu, Patrick Pittet, Kai Zhao. 367-370 [doi]
• Design of Reliable CMOS Phase-Locked LoopsChin-Long Wey, Chi-Shu Huang, Shaolei Quan. 371-374 [doi]
• Novel Current Sensing Circuit for IDDQ TestingJeong-Beom Kim. 375-378 [doi]
• Algorithms for Compositions of Arithmetic Transforms and Their ExtensionsYu Pang, Katarzyna Radecka, Zeljko Zilic. 379-382 [doi]
• A Low-Power and Low Silicon Area Testable CMOS LNA Dedicated to 802.15.4 Sensor Network ApplicationsMikael Cimino, Magali De Matos, Hervé Lapuyade, Thierry Taris, Yann Deval, Jean-Baptiste Begueret. 383-386 [doi]
• Tamper Resistivity Analysis for Nano-meter LSI with Process VariationsMakoto Ikeda, Hiroshi Yamauchi, Kunihiro Asada. 387-390 [doi]
• Synthesis Method for BAW Filters ComputationJi Fan, Matthieu Chatras, Dominique Cros. 391-394 [doi]
• Reconfiguration of Bulk Acoustic Wave Filters: Application to WLAN 802.11b/g (2.40-2.48 GHz)Moustapha El Hassan, Eric Kerhervé, Yann Deval, Alexandre A. Shirakawa, Didier Belot. 395-398 [doi]
• Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI CircuitsSandro Sawicki, Renato Fernandes Hentschke, Marcelo de Oliveira Johann, Ricardo Reis. 399-402 [doi]
• Limits to a Correct Evaluation in RTD-based Ternary InvertersJuan Núñez, José M. Quintana, Maria José Avedillo. 403-406 [doi]
• Tunable photonic crystals using ferroelectric materialsLaurent Oyhenart, Valerie Vigneras. 407-410 [doi]
• Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparatorsJeroen De Maeyer, Pieter Rombouts, Ludo Weyten. 411-414 [doi]
• An Ultra Low Power Successive Approximation ADC with Selectable Resolution in 0.13 μm CMOS TechnologyAnna Arbat, Ángel Dieguez, Josep Samitier. 415-418 [doi]
• Optimizing Resistances and Capacitances of a Continuous-Time ΣΔ ADCLaurent de Lamarre, Marie-Minerve Louërat, Andreas Kaiser. 419-422 [doi]
• Pixel-level ADC by small charge quantum countingArnaud Peizerat, Marc Arques, Patrick Villard, Jean-Luc Martin, Gérard Bouvier. 423-426 [doi]
• Enhanced split-architecture delta-sigma ADCKyehyung Lee, Gabor C. Temes. 427-430 [doi]
• Generalized Analytical Design Equations for Variable Slope Class-E Power AmplifiersMustafa Acar, Anne-Johan Annema, Bram Nauta. 431-434 [doi]
• ACPR Performance Study for Modified LINC AmplifierMohamed A. Elaal, Fadhel M. Ghannouchi. 435-438 [doi]
• Issues on the Design of a Variable Power LINC Amplifier System in SiGe Operating at 2.4 GHzCharmaine Demanuele, Ivan Grech, Joseph Micallef, Edward Gatt. 439-442 [doi]
• Envelope/phase delays correction in an EER radio architectureJean-François Bercher, Corinne Berland. 443-446 [doi]
• Integrated MM-Wave MIMO Antenna with Directional Diversity using MEMS TechnologySylvain Ranvier, Clemens Icheln, Pertti Vainikainen, Fabien Ferrero, Cyril Luxey, Robert Staraj, Gilles Jacquemod. 447-450 [doi]
• A Robust Blind Image Watermarking Scheme in the SPIHT-Compressed Bit-StreamFouad Khelifi, Ahmed Bouridane, Fatih Kurugollu. 451-454 [doi]
• Contribution of Custom Instructions on SoPC for iris recognition applicationThomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara. 455-458 [doi]
• A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional InterpolationHossein Mahvash Mohammadi, J. M. Pierre Langlois, Yvon Savaria. 459-462 [doi]
• Coefficient, Pass and Code-Block Parallel Architecture for FBP Coding in JPEG2000Xin Fan, Chao Xu. 463-466 [doi]
• Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image ConvolutionGangadharan Deepak, Raveendranath Mahesh, Andrzej Sluzek. 467-470 [doi]
• Modeling and Design of the CMOS Boot-Strapped Inductor for 5-6 GHz ApplicationsDomenico Zito, Domenico Pepe, Bruno Neri, Graziella Scandurra. 471-474 [doi]
• Integrated RF Devices in Suspended TechnologyHervé Leblond, Dominique Baillargeat, Pierre Blondy. 475-477 [doi]
• Wide-Band Frequency-Independent Equivalent Circuit Model for Integrated Spiral Inductors in (Bi)CMOS TechnologyDomenico Zito, Domenico Pepe, Bruno Neri. 478-481 [doi]
• Performance of Si-Integrated Wide-Band Single-Ended Switched Capacitor ArraysLuís Mendes, João Caldinhas Vaz, Maria J. Rosário. 482-485 [doi]
• GA-SVM Optimization Kernel applied to Analog IC Design AutomationManuel F. M. Barros, Jorge Guilherme, Nuno Horta. 486-489 [doi]
• AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and FlowGonçalo Neves, Manuel F. M. Barros, Nuno Horta. 490-493 [doi]
• Impact of charge injection on system-level performance of a discrete-time GSM receiverRayan Mina, Jean-Charles Grasset, Jean-François Naviner. 494-497 [doi]
• A New Active Pixel Design using μc-Si TFT Technology to Improve Brightness Uniformity of Organic DisplaysArchanmael Gaillard, Régis Rogel, Samuel Crand, Taieb Mohammed-Brahim, Philippe Le Roy, Christophe Prat. 498-501 [doi]
• A Parallel-In Serial-Out Multiplier Using Redundant Representation for A Class of Finite FieldsAshkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi. 502-505 [doi]
• Delay Efficient 32-bit Carry-Skip AdderYu Shen Lin, Damu Radhakrishnan. 506-509 [doi]
• Request-skip adders : CMOS standard cell data dependent addersRobin Perrot, Nadine Azémard, Philippe Maurine. 510-513 [doi]
• Delay Optimized Redundant Binary AddersBijoy A. Jose, Damu Radhakrishnan. 514-517 [doi]
• Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full AddersMassimo Alioto, Gaetano Palumbo. 518-521 [doi]
• Implantable Smart Medical Microsystems: Limits and ChallengesMohamad Sawan. 522-524 [doi]
• Cryogenic SiGe Hetero-Junction Bipolar Transistors From Standard Technologies For Low Noise FLLDamien Prele, Gérard Sou, Geoffroy Klisnick, Michel Redon, Eric Breelle, Michel Piat, Fabrice Voisin. 525-528 [doi]
• Improved Chopper Stabilized Amplifier for Offset and 1/f Noise CancellationAndrea Agnes, Franco Maloberti, Giuseppe Martini. 529-532 [doi]
• Optimum Sizing and Compensation of Two-Stage CMOS Amplifiers Based On a Time-Domain ApproachRui Santos-Tavares, Nuno F. Paulino, João Goes, João P. Oliveira. 533-536 [doi]
• A 5.2-mW, 2.5-Gb/s Limiting Amplifer for OC-48 SONET ApplicationsKwisung Yoo, Gunhee Han, Sung Min Park. 537-540 [doi]
• Optimized Arithmetic Hardware Design based on Hierarchical Formal VerificationNikhil Kikkeri, Peter-Michael Seidel. 541-544 [doi]
• An Efficient H.264 VLSI Advanced Video EncoderKonstantinos Babionitakis, George Lentaris, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Gregory Doumenis, George Georgakarakos, John Sifnaios. 545-548 [doi]
• A VLSI Decoder for the Golden codeBarbara Cerato, Guido Masera, Emanuele Viterbo. 549-552 [doi]
• A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi DecoderWei-Li Su, Herming Chiueh. 553-556 [doi]
• RC-Chain: a Simple Model of Delay with a Ramp InputGiuseppe Di Cataldo, Rosario Mita, Gaetano Palumbo, Massimo Poli. 557-560 [doi]
• Error Detection Code Efficiency for Secure ChipsVincent Maingot, Régis Leveugle. 561-564 [doi]
• A Hybrid Method for the Recognition of Acceptor Splice SitesMahmood Akhtar, Eliathamby Ambikairajah, Julien Epps. 565-568 [doi]
• A Variable Duty Cycle with High-Resolution Synchronous Mirror DelayKai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang. 569-572 [doi]
• Optimized Design of a Digital IQ Demodulator Suitable for Adaptive Predistortion of 3rd Generation Base Station PAsChiheb Rebai, Haythem Ayari, Adel Ghazel, Slim Boumaiza, Fadhel M. Ghannouchi. 573-576 [doi]
• Design of Sampling-Based Downconversion Stage for Multistandard RF Subsampling ReceiverRim Barrak, Adel Ghazel, Fadhel M. Ghannouchi. 577-580 [doi]
• Shot-Noise Analysis in Circuits with Large Signal Excitations using Harmonic Balance SimulatorsMike Tempel, Georg Boeck. 581-583 [doi]
• Maximum frequency of operation of CMOS Static Frequency dividers: Theory and Design techniquesKaushik Sengupta, Hossein Hashemi. 584-587 [doi]
• Programmable Gain Amplifiers based on High-Linearity MOS Current DividersMaria Teresa Sanz, Santiago Celma, Belén Calvo. 588-591 [doi]
• Compact, low-power, analogue building blocks derived from MOSFETs translinear loopsMassimo Barbaro, Gian Nicola Angotzi. 592-595 [doi]
• Constant gm, rail-to-rail input transconductance stage with output common mode current compensationKirill Kozmin, Jonny Johansson. 596-599 [doi]
• New 1.5-V CMOS Current Feedback Operational AmplifierAhmed H. Madian, Soliman A. Mahmoud, Ahmed M. Soliman. 600-603 [doi]
• Simulating the Effects of Process Variations on Capacitive CrosstalkArani Sinha, Shahin Nazarian, T. M. Mak. 604-607 [doi]
• Power and Failure Analysis of CAM Cells Due to Process VariationsMahmoud Ben Naser, Csaba Andras Moritz. 608-611 [doi]
• An Embedded Rectifier-Based Built-In-Test Circuit for CMOS RF CircuitsGuoyan Zhang, Ronan Farrell. 612-615 [doi]
• System-Level ESD Protection Design with On-Chip Transient Detection CircuitCheng-Cheng Yen, Ming-Dou Ker, Pi-Chia Shih. 616-619 [doi]
• A Low-Power Highly Linear CMOS Transconductance TopologyHashem Zare-Hoseini, Izzet Kale, Richard C. S. Morling. 620-623 [doi]
• A Low-noise Low-offset Op Amp in 0.35μm CMOS ProcessZhineng Zhu, Raghu Tumati, Scott Collins, Rosemary Smith, David E. Kotecki. 624-627 [doi]
• Bandwidth Extension of High-Gain CMOS Stages Using Active Negative CapacitanceDavid J. Comer, Donald T. Comer, Jonathan B. Perkins, Kevin D. Clark, Adrian P. C. Genz. 628-631 [doi]
• A 1.5-V, Constant-Gm, Rail-to-Rail Input Stage Operational AmplifierAkram Masoom, Khayrollah Hadidi. 632-635 [doi]
• A Time-Consistent Video Segmentation Algorithm designed for Real-Time ImplementationMohammed El Hassani, Delphine Rivasseau, Stéphanie Jehan-Besson, Marinette Revenu, David Tschumperlé, Luc Brun, Marc Duranton. 636-639 [doi]
• Fuzzy classification, image segmentation and shape analysis for Human face detectionM. Ben Hmida, Yousra Ben Jemaa. 640-643 [doi]
• Research on An Improved Anisotropic High-pass Filtering Algorithm Based on the Step Angle SearchingQing Pan, Guoping Yan. 644-647 [doi]
• Unequal Error Protective and Standard Compatible Multiple Descriptions Coding for Image CommunicationArash Behgoo, Ali Aghagolzadeh, Mohammad Shahram Moin. 648-651 [doi]
• Comparison of Three Methods of Eliminating Musical Tones in Speech Denoising Subtractive TechniquesAnis Ben Aicha, Sofia Ben Jebara. 652-655 [doi]
• Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOSPeter Nilsson. 656-659 [doi]
• A New Transistor-Level Layout Generation Strategy for Static CMOS CircuitsCristiano Lazzari, Cristiano Santos, Ricardo Reis. 660-663 [doi]
• Analysis of the intermodulation distortion and nonlinearity of common-base SiGeC HBTsFarah Guillot, Patrice Garcia, Mireille Mouis, Didier Belot. 664-667 [doi]
• A High speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13μm CMOSBert Serneels, Michiel Steyaert, Wim Dehaene. 668-671 [doi]
• Broadband Modelling of a High Efficiency Rectenna for Batteryless RFID SystemsAlexandre Douyere, Jean-Daniel Lan Sun Luk, Alain Celeste, Frédéric Alicalapa. 672-675 [doi]
• Analysis and optimization of power line coupling circuit for CENELEC-PLC ModemKamel Fezzani, Chiheb Rebai, Adel Ghazel. 676-679 [doi]
• Analog Circuits for Symbol-Likelihood ComputationMatthias Frey, Hans-Andrea Loeliger, Patrick Merkli. 680-683 [doi]
• A Simple Method for Transmission with Reduced Crosstalk and EchoFrédéric Broydé, Evelyne Clavelier. 684-687 [doi]
• Benefits of prior speech segmentation for best time-frequency visualisation using Renyi's entropyDaoud Boutana, Messaoud Benidir. 688-691 [doi]
• A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction MechanismAndreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis. 692-695 [doi]
• Arithmetic Transforms of Imprecise Datapaths by Taylor Series ConversionYu Pang, Katarzyna Radecka, Zeljko Zilic. 696-699 [doi]
• Testing QCA Modular LogicSayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka. 700-703 [doi]
• Timing-Driven Redundant Contact Insertion for Standard Cell Yield EnhancementTetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. 704-707 [doi]
• Ultra-Small RLID Chip TechnologyMitsuo Usami. 708-711 [doi]
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• Effect of RF Front-End Parameters on UWB-OFDM Receiver Performances in Presence of Adjacent Channel InterferersPhilippe Lombard, Emilie Ponthus, Emil Novakov, Jean-Michel Fournier. 802-805 [doi]
• Two-Dimensional FIR Signal Adapted Filter BanksV. S. Sheeba, Elizabeth Elias. 806-809 [doi]
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• Ultra low voltage CMOS gatesYngvar Berg, Omid Mirmotahari, Per Andreas Norseng, Snorre Aunet. 818-821 [doi]
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• Accuracy Improvement by Nonlinearity Reduction in Two-Frequency Laser Heterodyne InterferometerShahram Mohammad Nejad, Saeed Olyaee. 914-917 [doi]
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• Design and Test of a CMOS MLP Analog Neural Network for Fast On-Board Signal ProcessingLaurent Gatet, Hélène Tap-Béteille, Marc Lescure. 922-925 [doi]
• An Analog-Digital Neural Processor for Integrated Sensor ConditioningNicolas Medrano, Maria Teresa Sanz, Pedro A. Martínez, Santiago Celma, Guillermo Zatorre. 926-929 [doi]
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• Design of a modular and mixed neuromimetic ASICJean Tomas, Yannick Bornat, Sylvain Saïghi, Timothée Levi, Sylvie Renaud. 946-949 [doi]
• A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization MethodologyRaf Schoofs, Tom Eeckelaert, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen. 950-953 [doi]
• A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage FeedbackManuel Sanchez-Renedo, Susanna Patón, Luis Hernández. 954-957 [doi]
• On the calibration of AD and DA converters based on R/�?R ladder networksCarmine Ciofi, Graziella Scandurra, Giuseppe Campobello, Gianluca Cannata. 958-961 [doi]
• Continuous-Time Complex Bandpass Modulator: Key Component for Highly Digitized ReceiverNejmeddine Jouida, Chiheb Rebai, Adel Ghazel, Dominique Dallet. 962-965 [doi]
• Scaling Input Signal Swings of Overloaded Integrators in Resonator-based Sigma-Delta ModulatorsUmut Yazkurt, Günhan Dündar, Selçuk Talay, Nicolas Beilleau, Hassan Aboushady, Laurent de Lamarre. 966-969 [doi]
• Secured and Seamless Handoff in Wireless Fourth Generation SystemsFaouzi Zarai, Noureddine Boudriga, Mohammad S. Obaidat. 970-973 [doi]
• Design and Implementation in FPGA of a MIMO Decoder for a 4G Wireless ReceiverAlberto Jimenez-Pacheco, Angel Fernandez Herrero, Javier Casajús-Quirós. 974-977 [doi]
• On the Use of a Performance Indicator for Optimal Pilot Positioning in Multicarrier SystemsDavid Bueche, Patrick Corlay, Marc Gazalet, François-Xavier Coudoux, Marc Slachciak. 978-981 [doi]
• Telecommunication synchronisation developpement based on high level virtual prototypeGuilleminot Celine, Laurent Andrieux. 982-985 [doi]
• A Low Complexity Simulation Algorithm for TH-UWB MMSE RAKE Receiver in NLOS ChannelMarina M. Marjanovic, José Manuel Páez-Borrallo. 986-990 [doi]
• A 3-bits DDS Oriented Low Power Consumption 15 GHz Phase Accumulator in a 0.25 μm BiCMOS SiGe: C TechnologyStephane Thuries, Eric Tournier, Jacques Graffeuil. 991-994 [doi]
• A Digital Frequency Shift Keying DemodulatorGérald Arnould, Fabrice Monteiro, Abbas Dandache. 995-998 [doi]
• RF Digital Predistorter for Power Amplifiers of 3G Base StationsAnouar Benchahed, Adel Ghazel, Mohamed Mabrouk, Chiheb Rebai, Fadhel M. Ghannouchi. 999-1002 [doi]
• A 20-GHz and 46-GHz, 32x6-bit ROM for DDS Application in InP DHBT TechnologySanjeev Manandhar, Steven E. Turner, David E. Kotecki. 1003-1006 [doi]
• 4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOSMasahiro Sasaki, Makoto Ikeda, Kunihiro Asada. 1007-1010 [doi]
• 79 GHz Fully Integrated Fully Differential Si/SiGe HBT Amplifier for Automotive Radar ApplicationsSebastien Chattier, Bernd Schleicher, Till Feger, Tatyana Purtova, Hermann Schumacher. 1011-1014 [doi]
• A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer RejectionAndrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani. 1015-1018 [doi]
• A 4mA, 0.25 SiGe, 23GHz BiFET Low Noise AmplifierThierry Taris, Nicolas Seller, Romaric Toupe, Hervé Lapuyade, Jean-Baptiste Begueret, Yann Deval. 1019-1022 [doi]
• A Dual Stage GaAs Amplifier for a K-Band Direct ReceiverMeik Huber, Stefan von der Mark, Georg Boeck. 1023-1025 [doi]
• Low Power 38-GHz UWB Tunable LNA Design Using SiP TechnologyYang Chuan Chen, Chun-Hsing Li, J. K. Huang, Chien-Nan Kuo, Yu-Ting Cheng. 1026-1029 [doi]
• Compact Modeling and Applications of CNTFETs for Analog and Digital Circuit DesignFabien Prégaldiny, Jean-Baptiste Kammerer, Christophe Lallement. 1030-1033 [doi]
• A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire TransistorsAntoine Jalabert, Fabien Clermidy, Amara Amara. 1034-1037 [doi]
• 3D simulation of thin-film bulk acoustic wave resonators (FBAR)Sylvain Giraud, Stephane Bila, Michel Aubourg, Dominique Cros. 1038-1041 [doi]
• An Improved Isolation W-CDMA Ladder BAW-SMR FilterAlexandre A. Shirakawa, Jean-Marie Pham, Pierre Jarry, Eric Kerhervé, Jean-Baptiste David, Fabien Dumont, Didier Belot. 1042-1044 [doi]
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• Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic ComparisonDavid Bol, Jean-Didier Legat, José M. Quintana, Maria José Avedillo. 1049-1052 [doi]
• Pre-conditioning Free Footless DCVSL for High-performance DatapathsMakoto Ikeda, Kin Hooi Dia, Kunihiro Asada. 1053-1056 [doi]
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• Designing Analog Circuits with Reduced Biasing PowerReza Hashemian. 1069-1072 [doi]
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• A Systolic Inversion Architecture Based on Modified Extended Euclidean Algorithm for GF(2K) FieldsApostolos P. Fournaris, Odysseas G. Koufopavlou. 1081-1084 [doi]
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• Design techniques for very high speed digital delta-sigma modulators aimed at all-digital RE transmittersAntoine Frappe, Axel Flament, Andreas Kaiser, Bruno Stefanelli, Andreia Cathelin. 1113-1116 [doi]
• A Study of High-Frequency Bandpass Delta-Sigma Transmitter ArchitecturesNejdat Demirel, Eric Kerhervé, Renato Negra, Fadhel M. Ghannouchi. 1117-1120 [doi]
• A ΣΔ fractional- N synthesizer for GSM standard specificationsHassène Mnif, Mourad Fakhfakh, Ibtihel Krout, M. Barhoumi, Mourad Loulou. 1121-1124 [doi]
• A Programmable Complex FIR Filter with Integrated MEMS Filter for Front-end Charge Sampling ReceiverJames Wei, Dominique Morche, Serge Ramet, Jacques Verdier. 1125-1128 [doi]
• Direct Form I Active Optical Filters Realized in an Integrated Photonic ArchitectureDuncan L. MacFarlane, Jian Tong, Robert Hunt, Issa M. S. Panahi, Kent Wade. 1129-1132 [doi]
• A 100dB dynamic range CMOS image sensor with global shutterEstelle Labonne, Gilles Sicard, Marc Renaudin, Pierre-Damien Berger. 1133-1136 [doi]
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• A New Simple UWB Monocycle Pulse GeneratorAlexandre Serres, Yvan Duroc, Tan-Phu Vuong, Jose Ewerton P. de Farias, Glausco Fontgalland. 1212-1215 [doi]
• A Low-Power High-Rate Modulator for Ultra-Wideband TransmittersMehdi Salehi, Abdolreza Nabavi, Nader Ghadimi. 1216-1219 [doi]
• A Pre-processing Based Real-Time Address Tracer for Embedded MicroprocessorsYuan-Long Jeang, Tzuu-Shaang Wey, Hung-Yu Wang, Ching-Ta Chen. 1220-1223 [doi]
• Efficient Post-Processing Module for a Chaos-based Random Bit GeneratorTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. 1224-1227 [doi]
• Hardware-Software Co-design of a Dynamically Reconfigurable FPGA-based Fuzzy Logic ControllerFrancisco Fons, Mariano Fons, Enrique Cantó. 1228-1231 [doi]
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• MAC Protocol for Low-Power Real-Time Wireless Sensing and ActuationJose A. Afonso, Luis A. Rocha, Helder R. Silva, Jose Higino Correia. 1248-1251 [doi]
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• A 900 MHz Multiphase LC Oscillator with Sinusoidal Outputs in SiGe TechnologyRaúl Regidor, Roberto Esper-Chaín, Félix Tobajas, Octavio Santana, Roberto Sarmiento. 1256-1259 [doi]
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• Application of the inductor multiplierTakeshi Shima. 1264-1267 [doi]
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