Yuan-Long Jeang - researchr alias

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Viewing Publication 1 - 17 from 17

2010

2006

Design of a Dynamic PCM Selector for Non-deterministic EnvironmentLiang-Bi Chen, Ing-Jer Huang, Yuan-Long Jeang. apccas 2006: 1124-1127 [doi]

A Single-Stream Pipelined Instruction Decompression System for Embedded MicroprocessorsYuan-Long Jeang, Tzuu-Shaang Wey, Hung-Yu Wang, Chih-Chung Tai. iih-msp 2006: 571-574 [doi]

A New and Efficient Field-Partition Based Code Compression and Its Pipelined Decompression SystemYuan-Long Jeang, Chih-Chung Tai, Yong-Zong Lin. icicic 2006: 10-13 [doi]

A Methodology Based on Maximal-Profit Spanning Tree for Designing Application Specific Networks on Chip (ASNOC)Yuan-Long Jeang, Chung-Wei Hung, Chuen-Muh Chiang. icicic 2006: 18-21 [doi]

A New and Efficient Real-Time Address Tracer for Embedded MicroprocessorsYuan-Long Jeang, Ching-Ta Chen, Chih-Chung Tai. icicic 2006: 14-17 [doi]

A New EmbeddedWavelet Image Coding Based on Zero-block and Array (N-EZBA) and Its Efficient Hardware ImplementationYuan-Long Jeang, Ping-Shou Cheng, Jiun-Hau Tu, Kai-Jyun Liang, Ching-Ta Chen. icicic 2006: 6-10 [doi]

A Pre-processing Based Real-Time Address Tracer for Embedded MicroprocessorsYuan-Long Jeang, Tzuu-Shaang Wey, Hung-Yu Wang, Ching-Ta Chen. icecsys 2006: 1220-1223 [doi]

2005

A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)Yuan-Long Jeang, Jer Min Jou, Win-Hsien Huang. ieicet, 88-A(12):3531-3538, 2005. [doi]

2003

Design of FPGA-based adaptive remote calibration control systemYuan-Long Jeang, Liang-Bi Chen, Chia-Pin Huang, Yu-Hsiang Hsu, Ming-Yu Yeh, Kai-Ming Yang. fpt 2003: 299-302 [doi]

An embedded in-circuit emulator generator for SOC platformYuan-Long Jeang, Liang-Bi Chen, Yi-Ting Chou, Hsin-Chia Su. fpt 2003: 315-318 [doi]

2002

An optimal PCM codec soft IP generator and its applicationGwo-Yang Wu, Liang-Bi Chen, Yuan-Long Jeang, Gwo-Jia Jong. fpt 2002: 315-317 [doi]

1993

High throughput pipelined data path synthesis by conserving the regularity of nested loopsYuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee. iccad 1993: 450-453 [doi]

The determination of the cycle length in high level synthesisMing-Hwa Sheu, Yuan-Long Jeang, Jhing-Fa Wang, Jau-Yien Lee. integration, 16(2):131-148, 1993. [doi]

1991

On the Performance Guarantees of the Minimum Multisets Binding (MMB) ProblemYuan-Long Jeang, Jhing-Fa Wang, Jau-Yien Lee. jise, 7(2):203-215, 1991. [doi]

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