Damu Radhakrishnan - researchr alias

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Viewing Publication 1 - 19 from 19

2009

Redundant binary partial product generators for compact accumulation in Booth multipliersBijoy A. Jose, Damu Radhakrishnan. mj, 40(11):1606-1612, 2009. [doi]

2008

Delay Efficient 32-Bit Carry-Skip AdderYu Shen Lin, Damu Radhakrishnan. vlsi, 2008, 2008. [doi]

2006

Delay Optimized Redundant Binary AddersBijoy A. Jose, Damu Radhakrishnan. icecsys 2006: 514-517 [doi]

Delay Efficient 32-bit Carry-Skip AdderYu Shen Lin, Damu Radhakrishnan. icecsys 2006: 506-509 [doi]

2004

Experimental Analysis of Batteries Under Continuous and Intermittent OperationsS. Castillo, Naveen K. Samala, K. Manwaring, Baback A. Izadi, Damu Radhakrishnan. csreaESA 2004: 18-24

A Low-Power Pipelined Implementation of 2D Discrete Wavelet TransformYong Liu, Edmund Ming-Kit Lai, A. Benjamin Premkumar, Damu Radhakrishnan. csreaESA 2004: 40-46

Switching Activity Minimization in Combinational Logic DesignR. V. Menon, S. Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi. csreaESA 2004: 47-53

Shift Invert Coding (SINV) for Low Power VLSIJayapreetha Natesan, Damu Radhakrishnan. dsdm 2004: 190-194 [doi]

A Novel Bus Encoding Technique for Low Power VLSIJayapreetha Natesan, Damu Radhakrishnan. csreaESA 2004: 54-62

A Low Energy Deep Sub-Micron Bus Coding TechniqueNaveen K. Samala, Damu Radhakrishnan, Baback A. Izadi. csreaESA 2004: 25-30

2003

Power Optimized Combinational Logic DesignR. V. Menon, S. Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi. csreaESA 2003: 223-227

Low-Power Dynamic Scheduling in Heterogeneous SystemsSaumya Uppaluri, Baback A. Izadi, Damu Radhakrishnan. csreaESA 2003: 261-267

2001

A high performance RNS multiply-accumulate unitA. P. Preethy, Damu Radhakrishnan, Amos Omondi. glvlsi 2001: 145-148 [doi]

Fault-tolerance scheme for an RNS MAC: performance and cost analysisA. P. Preethy, Damu Radhakrishnan, Amos Omondi. iscas 2001: 717-720 [doi]

2000

Pass logic circuits with reduced switching activity for low power DSP processorsDamu Radhakrishnan. icassp 2000: 3327-3330 [doi]

1999

A Parallel Approach to Direct Analog-to-Residue ConversionDamu Radhakrishnan, A. P. Preethy. ipl, 69(5):249-252, 1999. [doi]

1998

A new approach to data conversion: direct analog-to-residue converterDamu Radhakrishnan, Adimathara P. Preethy. icassp 1998: 3013-3016 [doi]

1990

Fault tolerance in RNS: an efficient approachDamu Radhakrishnan, Taejin Pyon. iccd 1990: 41-44 [doi]

1985

Multiple Output Pass Networks: Design and TestingAli Feizi, Damu Radhakrishnan. itc 1985: 907-911

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