Abstract is missing.
- Practical approaches to the verification of a telecom megacell using FormalCheckLeila Barakatain, Sofiène Tahar, Jean Lamarche, Jean-Marc Gendreau. 1-6 [doi]
- A novel reseeding technique for accumulator-based test pattern generationXrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos. 7-12 [doi]
- ITEM: an iterative improvement test generation procedure for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. 13-18 [doi]
- Solving large scale assignment problems in high-level synthesis by approximative quadratic programmingFlorin Balasa, Werner Geurts, Francky Catthoor, Hugo De Man. 19-24 [doi]
- Layout aware retimingAbhishek Ranjan, Ankur Srivastava, V. Karnam, Majid Sarrafzadeh. 25-30 [doi]
- Optimal partitioning and balanced scheduling with the maximal overlap of data footprintsZhong Wang, Edwin Hsing-Mean Sha, Yuke Wang. 31-36 [doi]
- SOI for asynchronous dynamic circuitsRajiv V. Joshi, Wei Hwang, Ching-Te Chuang. 37-42 [doi]
- Leakage control and tolerance challenges for sub-0.1µm microprocessor circuitsRam Krishnamurthy, Mark Anders, K. Soumyanath, Shekhar Borkar. 43-44 [doi]
- Challenges in integrated CMOS transceivers for short distance wirelessKhurram Muhammad, Robert B. Staszewski, Poras T. Balsara. 45-50 [doi]
- An accurate evaluation of routing density for symmetrical FPGAsNak-Woong Eum, Taewhan Kim, Chong-Min Kyung. 51-55 [doi]
- Preferred direction Steiner treesMehmet Can Yildiz, Patrick H. Madden. 56-61 [doi]
- Faster and more accurate wiring evaluation in interconnect-centric floorplanningHung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang. 62-67 [doi]
- Global objectives for standard cell placementMehmet Can Yildiz, Patrick H. Madden. 68-72 [doi]
- A circuit level implementation of an adaptive issue queue for power-aware microprocessorsAlper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook. 73-78 [doi]
- A CORDIC based array architecture for complex discrete wavelet transformBipul Das, Swapna Banerjee. 79-84 [doi]
- A VLSI wrapped wave front arbiter for crossbar switchesJosé G. Delgado-Frias, Girish B. Ratanpal. 85-88 [doi]
- Effective algorithms for cache-level compressionEdward Ahn, Seung-Moon Yoo, Sung-Mo Kang. 89-92 [doi]
- 2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-testSeung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang. 93-96 [doi]
- Rarity based guided state space searchMalay K. Ganai, Adnan Aziz. 97-102 [doi]
- Who are the alternative wires in your neighborhood? (alternative wires identification without search)Chih-Wei Jim Chang, Malgorzata Marek-Sadowska. 103-108 [doi]
- Hierarchical model order reduction for signal-integrity interconnect synthesisYu-Min Lee, Charlie Chung-Ping Chen. 109-114 [doi]
- An efficient model for frequency-dependent on-chip inductanceMin Xu, Lei He. 115-120 [doi]
- Models for power consumption and power grid noise due to datapath transition activityLijun Gao, Keshab K. Parhi. 121-126 [doi]
- Electronic devices, structures and transport in carbon based materials: molecular electronics and quantum computingDeepak Srivastava. 127 [doi]
- Single molecule electronicsMark C. Hersam. 128 [doi]
- Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowthJohn P. Denton, Sang Woo Pae, Gerold W. Neudeck. 129-132 [doi]
- Transistor sizing for reliable domino logic design in dual threshold voltage technologiesSeong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang. 133-138 [doi]
- Practical low-cost CPL implementations threshold logic functionsJosé M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas. 139-144 [doi]
- A high performance RNS multiply-accumulate unitA. P. Preethy, Damu Radhakrishnan, Amos Omondi. 145-148 [doi]
- A fast hybrid carry-lookahead/carry-select adder designOhsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka. 149-152 [doi]