Abstract is missing.
- Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS ResonatorsVenkiteswaran Anantharam, Maojiao He, Krishna Natarajan, Huikai Xie, Michael P. Frank. 5-11
- A Bus Encoding Scheme to Reduce Power Consuming Signal TransitionsAhmed Elkammar, Srinivasa Vemuru, Norman Scheinberg. 12-17
- Experimental Analysis of Batteries Under Continuous and Intermittent OperationsS. Castillo, Naveen K. Samala, K. Manwaring, Baback A. Izadi, Damu Radhakrishnan. 18-24
- A Low Energy Deep Sub-Micron Bus Coding TechniqueNaveen K. Samala, Damu Radhakrishnan, Baback A. Izadi. 25-30
- Low Power Sigma-Delta Modulator with Dynamic Biasing for Speech CODECsFun Ye, Jen-Shiun Chiang, Chun-Cheng Wu. 31-35
- Low-Power Switched-Capacitor Filters for Telecommunication ApplicationsCheng-Chih Chien, Jen-Shiun Chiang, Ming-Hung Tu, Yu-Cheng Sung, Yi-Tsung Lee. 36-39
- A Low-Power Pipelined Implementation of 2D Discrete Wavelet TransformYong Liu, Edmund Ming-Kit Lai, A. Benjamin Premkumar, Damu Radhakrishnan. 40-46
- Switching Activity Minimization in Combinational Logic DesignR. V. Menon, S. Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi. 47-53
- A Novel Bus Encoding Technique for Low Power VLSIJayapreetha Natesan, Damu Radhakrishnan. 54-62
- Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy ConsumptionKeith S. Vallerio, Niraj K. Jha. 63-69
- Link-Time Compaction of MIPS ProgramsMatias Madou, Bjorn De Sutter, Bruno De Bus, Ludo Van Put, Koen De Bosschere. 70-75
- Implementing Software Programs in FPGAs Using FlowpathsDarrin M. Hanna, Richard E. Haskell. 76-82
- Exploiting Symmetries for Optimal Integrated Code GenerationAndrzej Bednarski, Christoph W. Keßler. 83-92
- A New Fair Scheduling MAC Protocol for Wireless Sensor NetworksNiranjan Regatte, Carl Larsen, S. Jagannathan. 93-98
- Predictive Data Mining for Delinquency ModelingT. L. Bharatheesh, S. Sitharama Iyengar. 99-105
- Challenges in Monitoring Sensor Networks and a Solution FrameworkSheikh Iqbal Ahamed, Avinash Vyas. 106-112
- A Self-Organizing Wireless Sensor NetworkNader F. Mir. 113-122
- X32V: A Design of Configurable Processor Core for Embedded SystemsDavid Zier, Jumnit Hong, Savithri Venkatachalapathy, Jarrod Nelson, John Mark Matson, Ben Lee, Younghwan Bae, Hanjin Cho. 123-129
- RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded ComputingThomas Preußer, Steffen Köhler, Rainer G. Spallek. 130-135
- Admission Control for Dynamic Software Reconfiguration in Systems of Embedded SystemsYing Qiao, Luqi. 136-144
- An Intelligent Communications Backplane ArchitectureJ. Willis, A. Gaur, S. Cannon. 145-150
- An Adaptive Superscalar Architecture for Embedded SystemsMars Lan, Morteza Biglari-Abhari. 151-156
- A Configurable System-on-Chip Architecture with Descriptors for Dynamic ReconfigurationSebastian Wallner. 157-163
- HiDRA: A New Architecture for Heterogeneous Embedded SystemsZoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic. 164-170
- Embedded Software for an Array of ProcessorsStephen Bique. 171-175
- Building A Custom System-On-A-ChipEnoch Hwang. 176-184
- Language Selection for Mobile Systems: Java, C, or Both?Keith S. Vallerio, Niraj K. Jha. 185-191
- Identifying and Evaluating a Generic Set of Superinstructions for Embedded Java ProgramsDiarmuid O Donoghue, James F. Power. 192-198
- Realization of Platform Based on Java Technology for Embedded SystemsA-Qun Deng, Huan-Jun Yu, Shang-Xu Hu. 199-205
- Virtual Machine Code for Embedded SystemsSung-Lim Yun, Dong-Keun Nam, Se Man Oh, Jung Sook Kim. 206-214
- Scheduling Similarity-Constrained Real-Time TasksDeji Chen, Aloysius K. Mok. 215-221
- Embedded Systems for Real-Time Control of Differential Drive WMRJason Garbutt, Sabu John, Thurai Vinay. 222-228
- The Real-Time Implementations of AMR Codec for IMT-2000 SystemHyung Jung Kim, Deock Gu Jee, Man Ho Park, Byung Sik Yoon, Song In Choi. 229-232
- Synchronization in CAN-Based Embedded SystemsYe Su, Gurdip Singh. 233-239
- Best-Effort Scheduling (m, k)-Firm Real-Time Tasks Based on the (m, k)-Firm Constraint Meeting ProbabilityKyong Hoon Kim, Jong Kim, Sung Je Hong. 240-248
- Performance Analysis Techniques in SOC DesignSuboh A. Suboh, Nikitas A. Alexandridis, Tarek A. El-Ghazawi. 249-255
- Flexible Internet Based Diagnostics of Embedded SystemsJan Traumueller. 256-262
- Analytical Analysis of Data and Decision Fusion in Sensor NetworksZille Huma Kamal, Mohammad Ali Salahuddin, Ajay K. Gupta, Mark Terwilliger, Vijay Bhuse, Benjamin Beckmann. 263-272
- Embedded Systems for Meteorological Sensor ApplicationsYoung Yee, Edward Vidal Jr.. 273-279
- Multimedia Architectures of Mobile PhonesAchim Ibenthal, Christoph Minkwitz, Mathias Lindner. 280-283
- A Software Linearization Technique Using Embedded Applications for Measuring Microwave Dielectric Response of MaterialsR. Athinarayanan, J. N. Dahiya, J. A. Roberts. 284-288
- DSP Implementations of 3D Sound System Using HRTFHyung Jung Kim, Deock Gu Jee, Man Ho Park, Byung Sik Yoon, Song In Choi. 289-292
- Intelligent Resource Agents for Embedded SystemsEn-Hsin Huang, Tzilla Elrad. 293-302
- A Scalable Coprocessor for Bioinformatic Sequence AlignmentsScott F. Smith 0002. 303-308
- Novel Quantum Computer Emulator ChipJohn Robert Burger. 309-315
- Repair of the Genetic Material in Biologically Inspired Embryonic-Cell-Based SystemsX. Zhang, Gabriel Dragffy, Anthony G. Pipe. 316-324
- Performance/Energy Efficiency Analysis of Register Files in Superscalar ProcessorsShahzad Nazar, Behrooz Shirazi, Sungyong Jung. 325-331
- Survey and Evaluation of Low-Power Full-Adder CellsAhmed Sayed, Hussain Al-Asaad. 332-338
- A 4GHz Low-Power Folded-Cascode CMOS LC Quadrature VCO for RF TransceiversS. M. Rezaul Hasan, Nazmul Ula. 339-342
- Area- and Power-Reduced Standard-Cell Spanning Tree AddersPasquale Corsonello, Stefania Perri, Vitit Kantabutra. 343-352
- Fault-Tolerance Analysis of Some Sorting Networks for Single and Multiple PassesDer-Haw Wang, Salam N. Salloum. 353-359
- An Investigation of Non-Linear Machines as PRPGs in BISTJing Zhong, Jon C. Muzio. 360-366
- An Automated Algorithm for Partitioning Sequential VLSI CircuitsBassam Shaer, Kailash Aurangabadkar. 367-373
- Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based TestYinhe Han, Xiaowei Li. 374-381
- VLSI Issues for the Implementation of 10GBASE-T EthernetStephen Bates. 382-386
- Reliability Modelling of Embedded System-in-a-Package: Design and Packaging IssuesNagendra Bhargava Bharatula, Stijn Ossevoort, Paul Lukowicz, Gerhard Tröster. 387-392
- Approaches for Monitoring Vectors on Microprocessor BusesHector Arteaga, Hussain Al-Asaad. 393-398
- Automatic Extraction of Non-Iterated System Behavior from Verilog SpecificationsLubomir Ivanov. 399-406
- Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum ThroughputScott C. Smith. 407-412
- High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic MathematicsHimanshu Thapliyal, Hamid R. Arabnia. 413-416
- A High Performance, Low Area Overhead Carry Lookahead AdderJames Levy, Jabulani Nyathi. 417-426
- High Radix Modular Multiplication of Large Integers Optimised with Respect to Area and TimeViktor Bunimov, Manfred Schimmler. 427-433
- A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic MathematicsHimanshu Thapliyal, Hamid R. Arabnia. 434-439
- A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic MathematicsHimanshu Thapliyal, Hamid R. Arabnia. 440-446
- Design of a NULL Convention Self-Timed DividerScott C. Smith. 447-453
- A 2.4GHz CMOS Direct Down-Conversion MixerJie Long, Robert J. Weber. 454-457
- Feedback Techniques for Dual-Rail Self-Timed CircuitsRonald F. DeMara, Amit Kejriwal, Jude Seeber. 458-464
- Impact of Gate Leakage on the Performance of Analog Integrated Circuits - A Simulation StudyKamala Hariharan, Shoba Krishnan, V. P. Gopinath. 465-474
- A Design Methodology for Self-Timed Event Logic PipelinesXin Jia, Ranga Vemuri. 475-479
- A New Reversible Logic Gate and its ApplicationsD. P. Vasudevan, Parag K. Lala. 480-484
- A Graph Approach to Two-Level Logic MinimizationKazuya Shinozuka. 485-490
- BDD Minimization Using Graph Parameter PermutationP. W. Chandana Prasad, Ali Assi, Mohamed Raseen. 491-496
- A Fast Hierarchical Approach to FPGA PlacementPeng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji. 497-503
- High Performance Single Chip Implementation for a Digital Protective Relay Using FPGAJong Kang Park, Jong-Tae Kim, Myung Chul Shin. 504-508
- Design of Neural Network on FPGAS. P. Joy Vasantha Rani, P. Kanagasabapathy. 509-512
- Quantum Gates Revisited: A Tensor Product Based Interpretation ModelChao-Ming Tseng, Chih-Sheng Chen, Chua-Huang Huang. 513-522
- A Novel Segmented Parabolic Sine Approximation for Direct Digital Frequency SynthesizersDavid J. Betowski, Daniel Dwyer, Valeriu Beiu. 523-529
- An H-Tree Based Configuration Scheme for Reconfigurable DSP HardwareAndy Widjaja, José G. Delgado-Frias. 530-535
- A Distributed FIFO Scheme for System on Chip Inter-Component CommunicationRay Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias. 536-540
- Optimal Practical Perceptron Addition Application to Single Electron TechnologyValeriu Beiu, Mawahib H. Sulieman. 541-550
- CMOS Implementation of Phase-Encoded Complex-Valued Artificial Neural NetworksHoward E. Michel, David Rancour, Sushanth Iringentavida. 551-557
- AES Crypto-Processor Design Supporting 128/192/256 Bits Input Key Length for Smart CardYunKyung Lee, Sangwoo Lee, Youngsae Kim. 558-563
- An Efficient VLSI Architecture for MC Interpolation in AVC Video CodingDeng Lei, Wen Gao, Ming-Zeng Hu, Zhenzhou Ji. 564-568
- An Efficient Divider Architecture over GF(2:::m:::) for Elliptic Curve CryptographySang-Woo Lee, Jeong-Nyeo Kim, Jong-Soo Jang. 569-576
- Low Power Heuristic Block-level Voltage/Frequency SchedulingLi-Chuan Weng, Xiaojun Wang, Alan P. Su, Bin Liu. 577-581
- A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL ModelsHamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali. 582-588
- Case Study: Compiler Comparison for an Embedded Cryptographical ApplicationE. Barteska, Christof Paar, Jan Pelzl, Volker Wittelsberger, Thomas J. Wollinger. 589-595
- A Computational Intellegence Approach for Parametrized SoC OptimizationSuboh A. Suboh, Nikitas A. Alexandridis. 596-600
- An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded SoftwareTat Kee Tan, Anand Raghunathan, Niraj K. Jha. 601-605
- FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-TChristian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber. 606-610
- Evaluating Communications in a Sensor-Actuator Network for AutomationKun Huang, Shivakumar Sastry. 611-617
- Automated Credit Oriented System for Computer Network AdministrationS. Omar. 618