High Performance Single Chip Implementation for a Digital Protective Relay Using FPGA - researchr publication

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Jong Kang Park, Jong-Tae Kim, Myung Chul Shin. High Performance Single Chip Implementation for a Digital Protective Relay Using FPGA. In Hamid R. Arabnia, Minyi Guo, Laurence Tianruo Yang, editors, Proceedings of the International Conference on Embedded Systems and Applications, ESA 04 & Proceedings of the International Conference on VLSI, VLSI 04, June 21-24, 2004, Las Vegas, Nevada, USA. pages 504-508, CSREA Press, 2004.

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