An Efficient Hardware Implementation of a Robust and Low-Complexity ADSRC Timing Synchronization Design

Huynh Trong Anh, Jinsang Kim, Won-Kyung Cho, Jongchan Choi. An Efficient Hardware Implementation of a Robust and Low-Complexity ADSRC Timing Synchronization Design. In 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006. pages 1288-1291, IEEE, 2006. [doi]

Abstract

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