Abstract is missing.
- A Self-adaptive communication protocol allowing fine tuning between flexibility and performance in Homogeneous MPSoC systemsRémi Busseuil, Gabriel Marchesan Almeida, Sameer Varyani, Pascal Benoit, Gilles Sassatelli. 1-5
- Instruction Set Simulator for MPSoCs based on NoCs and MIPS ProcessorsLeandro Möller, André Rodrigues, Fernando Moraes 0001, Leandro Soares Indrusiak, Manfred Glesner. 7-11
- Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based MultiprocessorsDiana Goehringer, Jonathan Obie, Michael Hübner 0001, Jürgen Becker 0001. 13-20
- Novel Approach for Modeling Very Dynamic and Flexible Real Time ApplicationsIsmail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid. 21-27
- New Three-level Resource Management for Off-line Placement of Hardware Tasks on Reconfigurable DevicesIkbel Belaid, Fabrice Muller, Maher Benjemaa. 29-36
- Exploration of Heterogeneous FPGA ArchitecturesUmer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez. 37-44
- Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power ManagementChristian Schuck, Bastian Haetzer, Jürgen Becker 0001. 45-50
- Practical Resource Constraints for Online SynthesisStefan Döbrich, Christian Hochberger. 51-58
- ISRC: a runtime system for heterogeneous reconfigurable architecturesFlorian Thoma, Jürgen Becker 0001. 59-65
- A Self-Checking HW Journal for a Fault Tolerant Processor ArchitectureMohsin Amin, Camille Diou, Fabrice Monteiro, Abbas Ramazani, Abbas Dandache. 67-71
- A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-ChipOnur Derin, Erkan Diken. 73-78
- Dynamic Reconfigurable Computing: the Alternative to Homogeneous Multicores under Massive Defect RatesMonica Magalhães Pereira, Luigi Carro. 79-86
- An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph ApplicationsNachiket Kapre, André DeHon. 87-94
- Investigation of Digital Sensors for Variability Characterization on FPGAsFlorent Bruguier, Pascal Benoit, Lionel Torres. 95-100
- Investigating Self-Timed Circuits for the Time-Triggered ProtocolMarkus Ferringer. 101-108
- First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer TomographyMatthias Birk, Clemens Hagner, Matthias Balzer, Nicole V. Ruiter, Michael Hübner 0001, Jürgen Becker 0001. 109-114
- ECDSA Signature Processing over Prime Fields for Reconfigurable Embedded SystemsBenjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker 0001. 115-120
- A Secure Keyflashing Framework for Access Systems in Highly Mobile DevicesAlexander Klimm, Benjamin Glas, Matthias Wachs, Jürgen Becker 0001, Klaus D. Müller-Glaser. 121-126
- Session Teaching Reconfigurable Processor: the Biniou ApproachLoïc Lagadec, Damien Picard, Pierre-Yves Lucas. 127-134
- Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for EducationCédric Killian, Camel Tanougast, M. Monteiro, Camille Diou, Abbas Dandache, S. Jovanovic. 135-139
- Experimental Fault Injection based on the Prototyping of an AES CryptosystemJean-Baptiste Rigaud, Jean-Max Dutertre, Michel Agoyan, Bruno Robisson, Assia Tria. 141-147
- Reducing FPGA Reconfiguration Time Overhead using Virtual ConfigurationsMing Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch. 149-152
- Timing Synchronization for a Multi-Standard Receiver on a Multi-Processor System-onChipRoberto Airoldi, Fabio Garzia, Jari Nurmi. 153-155
- Mesh and Fat-Tree comparison for dynamically reconfigurable applicationsLudovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny. 157-160
- Technology Independent, Embedded Logic Cores Utilizing synthesizable embedded FPGA-cores for ASIC design validationJoachim Knäblein, Claudia Tischendorf, Erik Markert, Ulrich Heinkel. 161-168
- A New Client Interface Architecture for the Modified Fat Tree (MFT) Network-on-Chip (NoC) TopologyAbdelhafid Bouhraoua, Muhammad E. S. Elrabaa. 169-172
- Implementation of Conditional Execution on a Coarse-Grain Reconfigurable ArrayFabio Garzia, Roberto Airoldi, Jari Nurmi. 173-174
- Dynamically Reconfigurable Architectures for High Speed Vision SystemsOmer Kilic, Peter Lee. 175-177
- Virtual SoPC rad-hardening for satellite applicationsLudovic Barrandon, Thierry Capitaine, Loïc Lagadec, Nathalie Julien, Christophe Moy, Thierry Monédière. 179-180