Table of Contents

• Aging analysis of circuit timing considering NBTI and HCIDominik Lorenz, Georg Georgakos, Ulf Schlichtmann. 3-8 [doi]
• Built-in aging monitoring for safety-critical applicationsJulio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira. 9-14 [doi]
• An I-IP based approach for the monitoring of NBTI effects in SoCsC. Guardiani, A. Shibkov, Angelo Brambilla, Giancarlo Storti Gajani, Davide Appello, F. Piazza, Paolo Bernardi. 15-20 [doi]
• A methodology for measuring transistor ageing effects towards accurate reliability simulationElie Maricau, Georges G. E. Gielen. 21-26 [doi]
• Comparing transient-fault effects on synchronous and on asynchronous circuitsRodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis. 29-34 [doi]
• Invariant checkers: An efficient low cost technique for run-time transient errors detectionCarmela Noro Grando, Carlos Arthur Lang Lisbôa, Alvaro Freitas Moreira, Luigi Carro. 35-40 [doi]
• Towards automated fault pruning with Petri NetsPaolo Maistri, Régis Leveugle. 41-46 [doi]
• A low-cost solution for developing reliable Linux-based space computers for on-board data handlingMassimo Violante, M. L. Esposti. 49-54 [doi]
• Nonlinear compression functions using the MISR approach for security purposes in automotive applicationsEberhard Böhl, Paul Duplys. 55-60 [doi]
• Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faultsCaroline Concatto, Pedro Almeida, Fernanda Lima Kastensmidt, Érika F. Cota, Marcelo Lubaszewski, Marcos Herve. 61-66 [doi]
• Evaluating Alpha-induced soft errors in embedded microprocessorsPaolo Rech, Simone Gerardin, Alessandro Paccagnella, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Davide Appello. 69-74 [doi]
• Enhanced self-configurability and yield in multicore gridsEleftherios Kolonis, Michael Nicolaidis, Dimitris Gizopoulos, Mihalis Psarakis, Jacques Henri Collet, Piotr Zajac. 75-80 [doi]
• Online error detection and correction of erratic bits in register filesXavier Vera, Jaume Abella, Javier Carretero, Pedro Chaparro, Antonio González. 81-86 [doi]
• Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAsNiccolò Battezzati, Filomena Decuzzi, Massimo Violante, Michel Briet. 89-94 [doi]
• Exploiting embedded FPGA in on-line software-based test strategies for microprocessor coresMichelangelo Grosso, Matteo Sonza Reorda. 95-100 [doi]
• Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAsJosé Rodrigo Azambuja, Fernando Sousa, Lucas Rosa, Fernanda Lima Kastensmidt. 101-106 [doi]
• Novel DRAM mitigation techniqueAntonin Bougerol, Florent Miller, Nadine Buard. 109-113 [doi]
• SRAM cell design using tri-state devices for SEU protectionYuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou. 114-119 [doi]
• Critical charge characterization in 6-T SRAMs during read modeSebastiàn A. Bota, Gabriel Torrens, Bartomeu Alorda. 120-125 [doi]
• Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Chris Papachristou. 129 [doi]
• A fast error correction technique for matrix multiplication algorithmsCostas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro. 133-137 [doi]
• Soft error detection and correction for FFT based convolution using different block lengthsPedro Reviriego, Juan Antonio Maestro, Anne O Donnell, Chris J. Bleakley. 138-143 [doi]
• In-depth analysis of digital circuits against soft errors for selective hardeningMario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena. 144-149 [doi]
• DFx for massively multiprocessorsXavier Vera. 153 [doi]
• Designing dependable multicore system with unreliable componentsVikas Chandra. 154 [doi]
• Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chipGilles Bizot, Nacer-Eddine Zergainoh, Nichael Nicolaidis. 155 [doi]
• Concurrent checking with split-parity codesMichael Richter, Michael Gössel. 159-163 [doi]
• Multilinear codes for robust error detectionZhen Wang, Mark G. Karpovsky, Berk Sunar. 164-169 [doi]
• Error detection in 2-D Discrete Wavelet lifting transformsShih-Hsin Hu, Jacob A. Abraham. 170-175 [doi]
• Highs and lows of radiation testingDan Alexandrescu, Anne-Lise Lhomme-Perrot, Erwin Schäfer, Cyrille Beltrando. 179 [doi]
• A generic platform for remote accelerated tests and high altitude SEU experiments on advanced ICs: Correlation with MUSCA SEP3 calculationsGuillaume Hubert, Raoul Velazco, Paul Peronnard. 180 [doi]
• Using test infrastructures for (remote) online evaluation of the sensitivity to SEUs of FPGAsAndré V. Fidalgo, Gustavo R. Alves, Manuel C. Felgueiras, Manuel G. Gericota. 181 [doi]
• Briefing power/reliability optimization in embedded software designFabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena. 185-186 [doi]
• Linear and nonlinear MISR operations for safety and security in automotive applicationsPaul Duplys, Eberhard Böhl. 187-188 [doi]
• FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tagsJunfeng Fan, Miroslav Knezevic, Dusko Karaklajic, Roel Maes, Vladimir Rozic, Lejla Batina, Ingrid Verbauwhede. 189-191 [doi]
• Error detection in addition chain based ECC Point MultiplicationSalvatore Pontarelli, Gian-Carlo Cardarilli, Marco Re, Adelio Salsano. 192-194 [doi]
• Detectability analysis of small delays due to resistive opens considering process variationsJose Luis Garcia-Gervacio, Víctor H. Champac. 195-197 [doi]
• Controllability and observability in mixed signal coresJose Rocha, Nuno Dias, Angelo Monteiro, Alexandre Neves, Gabriel Santos, Marcelino B. Santos, João Paulo Teixeira. 198-200 [doi]
• A fault tolerant journalized stack processor architectureAbbas Ramazani, Mohsin Amin, Fabrice Monteiro, Camille Diou, Abbas Dandache. 201-202 [doi]
• Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphersAlejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena. 203-205 [doi]
• An Input Vector Monitoring Concurrent BIST scheme exploiting Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis. 206-207 [doi]
• Analysis of the extra delay on interconnects caused by resistive opens and shortsPablo Maqueda, Josep Rius. 208-209 [doi]
• C-testable S-box implementation for secure advanced encryption standardHafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan. 210-211 [doi]
• Fault injection-based evaluation of a synchronous NoC routerAshkan Eghbal, Pooria M. Yaghini, Hossein Pedram, Hamid R. Zarandi. 212-214 [doi]
• A low-cost fault-tolerant technique for Carry Look-Ahead adderAlireza Namazi, Yasser Sedaghat, Seyed Ghassem Miremadi, Alireza Ejlali. 217-222 [doi]
• Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologiesJorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 223-228 [doi]
• Designing fault tolerant FSM by nano-PLASamary Baranov, Ilya Levin, Osnat Keren, Mark G. Karpovsky. 229-234 [doi]
• Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-testAmit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji. 237-242 [doi]
• On-line characterization and reconfiguration for single event upset variationsKenneth M. Zick, John P. Hayes. 243-248 [doi]
• Aggressively voltage overscaled adaptive RF systems using error control at the bit and symbol levelsJayaram Natarajan, Gokul Kumar, Shreyas Sen, Muhammad Mudassar Nisar, Deuk Lee, Abhijit Chatterjee. 249-254 [doi]
• An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encodersHoussein Jaber, Fabrice Monteiro, Abbas Dandache. 257-261 [doi]
• Ultra low cost asynchronous handshake checkerSteffen Zeidler, Marcus Ehrig, Milos Krstic, Michael Augustin, Christoph Wolf, Rolf Kraemer. 262-268 [doi]
• ATPG-based grading of strong fault-securenessMarc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker. 269-274 [doi]