Abstract is missing.
- Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based SystemsKatarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker. 1-6
- Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive CouplingTudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner. 7-14
- A Reconfigurable Cell for a Multi-Style Asynchronous FPGAPhilippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet. 15-22
- A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable SystemsLeandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes. 23-30
- Dynamic Relocation of Hybrid Tasks: A Complete Design FlowMarcelo Götz, Tao Xie 0004, Florian Dittmann. 31-38
- HS Scale: A run-time adaptable MP-SoC architectureNicolas Saint-Jean, Camille Jalier, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. 39-46
- System Level Design of a Dynamically Self-Reconfigurable Image Processing SystemKurt Franz Ackermann, Leandro Soares Indrusiak, Manfred Glesner. 47-54
- A Customizable LEON2-Based VLIW ProcessorPeter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner. 55-60
- Massively Parallel Processor Architectures: A Co-design ApproachHritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier. 61-68
- Stack processor architecture and development methods suitable for dependable applicationsMehdi Jallouli, Camille Diou, Fabrice Monteiro. 69-75
- Coordinated concurrent memory accesses on a reconfigurable multimedia processorSamar Yazdani, Joel Cambonie, Bernard Pottier. 76-83
- Experiences of Using Object Oriented Programming Methods in High Level Network-on-Chip and System-on-Chip DesignSanna Määttä, Jari Nurmi. 84-89
- Multiple Abstraction Views of FPGA to Map Parallel ApplicationsSébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser. 90-97
- A Dynamic Communication Structure for Dynamically Reconfigurable FPGAsSlavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber. 98-105
- Adaptive Network for Multiprocessing in Programmable Logic DevicesThomas Haller, Christophe Bobda. 106-110
- Long-Range Dependence and On-chip Processor TrafficAntoine Scherrer, Antoine Fraboulet, Tanguy Risset. 111-120
- FPGA Prototyping of a Scan Based System-On-Chip DesignBrendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook. 121-126
- Latch Inference for Equivalence CheckingAnatol Ursu. 127-131
- A Dependable Parallel Architecture for SBoxesGiorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 132-137
- IBC-EI: An Instruction Based Compression method with Encryption and Integrity CheckingEduardo Wanderley Netto, Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet. 138-145
- Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip MemoryRomain Vaslin, Guy Gogniat, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson. 146-153
- Self-adaptive Security at Application Level: a ProposalAlberto Ferrante, Antonio Vincenzo Taddeo, Mariagiovanna Sami, Fabrizio Mantovani, Jurijs Fridkins. 154-160
- FPGA Implemenatation of an Adaptive Filtering: Application on ECG Signal Artefact Suppression in MRI EnvironmentHervé Berviller, Vincent Frick, Philippe Bougeot, Jean-Philippe Blonde, Julien Oster, Jacques Felbinger. 161-165
- Implementation of a 2D low-pass image filtering algorithm on a reconfigurable deviceFabio Garzia, Claudio Brunelli, Andrea Ferro, Jari Nurmi. 166-170
- Special Purpose Multi-processor for On-line Fault Detection on Induction Motors during Steady StateJose Alberto Vite-Frias, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jesus Rooney Rivera-Guillen, Arturo Garcia-Perez. 171-176
- A Family of Ultra-Fine Grain CNTFET-based Reconfigurable Logic GatesJ. Liu, Ian O Connor, David Navarro, Frédéric Gaffiot. 177-185
- On the Design of a Reconfigurable Multiplier for Integer and Galois Field MultiplicationHeiko Hinkelmann, Tudor Murgan, G. Liu, Peter Zipf, Manfred Glesner. 185-191
- Automatic Generation of Adaptive Multiprocessor SystemsThomas Haller, José Rodrigo Azambuja, Christophe Bobda. 192-193
- Dedicated Multiprocessing Unit for Polynomial Evaluation on FPGA in CNC Profile GenerationJesus Rooney Rivera-Guillen, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jose Alberto Vite-Frias. 194-195
- Dedicated Special Purpose Multiprocessor System for the Diagnostic of Rotor Bar Breakage on Induction MotorsAlejandro Ordaz-Moreno, René de Jesús Romero-Troncoso, Jose Alberto Vite-Frias, Jesus Rooney Rivera-Guillen, Arturo Garcia-Perez. 196-197
- Selecting the Optimal Number of Functional Units of Digital Real Time SystemsWladyslaw Szczesniak. 198-199