Abstract is missing.
- Fast Adjustable NPN Classification using Generalized SymmetriesXuegong Zhou, Lingli Wang, Peiyi Zhao, Alan Mishchenko. 1-7 [doi]
- A SAT-based Timing Driven Place and Route Flow for Critical Soft IPHenri Fraisse, Dinesh Gaitonde. 8-15 [doi]
- Placement Strategies for 2.5D FPGA Fabric ArchitecturesChirag Ravishankar, Dinesh Gaitonde, Trevor Bauer. 16-20 [doi]
- Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution ModelYehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk. 21-25 [doi]
- Hierarchical Force-Based Block Spreading for Analytical FPGA PlacementDries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt. 26-29 [doi]
- Automatic Topology Optimization for FPGA Interconnect SynthesisAlex Rodionov, Jonathan Rose. 30-34 [doi]
- Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAsAndrew Boutros, Sadegh Yazdanshenas, Vaughn Betz. 35-42 [doi]
- Activation Function Architectures for FPGAsBogdan Pasca, Martin Langhammer. 43-50 [doi]
- FBNA: A Fully Binarized Neural Network AcceleratorPeng Guo, Hong Ma, Ruizhi Chen, Pin Li, Shaolin Xie, Donglin Wang. 51-54 [doi]
- ClosNets: Batchless DNN Training with On-Chip a Priori Sparse Neural TopologiesMihailo Isakov, Alan Ehret, Michel A. Kinsy. 55-59 [doi]
- RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural NetworksCheng Luo, Yuhua Wang, Wei Cao, Philip H. W. Leong, Lingli Wang. 60-63 [doi]
- A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration ArchitectureDi Wu, Jin Chen, Wei Cao, Lingli Wang. 64-67 [doi]
- Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAsIbrahim Ahmed, Shuze Zhao, James Meijers, Olivier Trescases, Vaughn Betz. 68-75 [doi]
- DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of CyclesDonggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, Krste Asanovic. 76-80 [doi]
- Enabling Low Impact, Rapid Debug for Highly Utilized FPGA DesignsRobert Hale, Brad L. Hutchings. 81-84 [doi]
- Fault Characterization Through FPGA UndervoltingBehzad Salami 0001, Osman S. Unsal, Adrián Cristal. 85-88 [doi]
- FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAsVladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott. 89-96 [doi]
- Customizing Low-Precision Deep Neural Networks for FPGAsJulian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland. 97-100 [doi]
- Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller InterfacesYongming Shen, Tianchu Ji, Michael Ferdman, Peter Milder. 101-105 [doi]
- In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASICEriko Nurvitadhi, Jeffrey J. Cook, Asit Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Shumarayev. 106-110 [doi]
- Resource Elastic Virtualization for FPGAs Using OpenCLAnuj Vaishnav, Khoa Dang Pham, Dirk Koch, James Garside. 111-118 [doi]
- Providing Multi-tenant Services with FPGAs: Case Study on a Key-Value StoreZsolt István, Gustavo Alonso, Ankit Singla. 119-124 [doi]
- Accelerating Database Systems Using FPGAs: A SurveyPhilippos Papaphilippou, Wayne Luk. 125-130 [doi]
- A Survey on FPGA VirtualizationAnuj Vaishnav, Khoa Dang Pham, Dirk Koch. 131-138 [doi]
- A Collaborative Framework for FPGA-based CNN Design Modeling and OptimizationJiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha. 139-146 [doi]
- Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGARuizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu. 147-154 [doi]
- Cascade^CNN: Pushing the Performance Limits of Quantisation in Convolutional Neural NetworksAlexandros Kouris, Stylianos I. Venieris, Christos-Savvas Bouganis. 155-162 [doi]
- Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGAJunsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, Deming Chen. 163-169 [doi]
- FastPath: Towards Wire-Speed NVMe SSDsAthanasios Stratikopoulos, Christos Kotselidis, John Goodacre, Mikel Luján. 170-177 [doi]
- FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit EthernetAndreas Oeldemann, Thomas Wild, Andreas Herkersdorf. 178-185 [doi]
- A Smart Network Interface Approach for Distributed Applications on Xilinx Zynq SoCsShanker Shreejith, Ryan A. Cooke, Suhaib A. Fahmy. 186-190 [doi]
- Accelerating MPI Message Matching through FPGA OffloadQingqing Xiong, Anthony Skjellum, Martin C. Herbordt. 191-195 [doi]
- Median Filtering with Very Large Windows: SKA Algorithms for FPGAsTyrone Sherwin, Kevin I-Kai Wang, Prabu Thiagaraj, Oliver Sinnen. 196-201 [doi]
- Accelerated Inference of Positive Selection on Whole GenomesNikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos, Dionisios N. Pnevmatikatos. 202-209 [doi]
- SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome SequencingJason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu. 210-214 [doi]
- Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA SystemsNina Engelhardt, C.-H. Dominic Hung, Hayden Kwok-Hay So. 215-218 [doi]
- High Performance Communication on Reconfigurable ClustersJiayi Sheng, Chen Yang, Martin C. Herbordt. 219-223 [doi]
- CIDPro: Custom Instructions for Dynamic Program DiversificationThinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew Kei Lam, Nandeesha Veeranna. 224-229 [doi]
- Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial ReconfigurationMarie Nguyen, James C. Hoe. 230-234 [doi]
- Case for Fast FPGA Compilation Using Partial ReconfigurationDongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon. 235-238 [doi]
- A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable ArchitecturesTakuya Kojima, Hideharu Amano. 239-242 [doi]
- Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable MemoriesAmeer M. S. Abdelhadi, Guy G. F. Lemieux, Lesley Shannon. 243-250 [doi]
- Weighted Group Decision Making Using Multi-identity Physical Unclonable FunctionsLake Bu, Michel A. Kinsy. 251-255 [doi]
- FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and AreaAnkit Wagle, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula. 256-259 [doi]
- Everyone's a Critic: A Tool for Exploring RISC-V ProjectsDustin Richmond, Michael Barrow, Ryan Kastner. 260-264 [doi]
- ILP-Based Modulo Scheduling and Binding for Register MinimizationPatrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch 0001. 265-271 [doi]
- Multi-fidelity Optimization for High-Level Synthesis DirectivesCharles Lo, Paul Chow. 272-279 [doi]
- Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level SynthesisJulian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Oliver Sinnen, Andreas Koch 0001. 280-286 [doi]
- Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point RepresentationHongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk. 287-294 [doi]
- Application Partitioning on FPGA Clusters: Inference over Decision Tree EnsemblesMuhsen Owaida, Gustavo Alonso. 295-300 [doi]
- Resource Reduction of BFGS Quasi-Newton Implementation on FPGA Using Fixed-Point Matrix UpdatingJia Liu, Qiang Liu. 301-306 [doi]
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable ComputingYaman Umuroglu, Lahiru Rasnayake, Magnus Själander. 307-314 [doi]
- A DSL-Based FFT Hardware Generator in ScalaFrançois Serre, Markus Püschel. 315-322 [doi]
- Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p)Debdeep Mukhopadhyay, Debapriya Basu Roy. 323-326 [doi]
- An Efficient Exact Fused Dot Product Processor in FPGALuis Fiolhais, Horácio C. Neto. 327-330 [doi]
- Efficient Multiple Constant Multiplication Using DSP Blocks in FPGAAhmet Can Mert, Hasan Azgin, Ercan Kalali, Ilker Hamzaoglu. 331-334 [doi]
- A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field GenerationMichael Barrow, Steven M. Burns, Ryan Kastner. 335-342 [doi]
- An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer GraphicsGeorgios Chatzianastasiou, George A. Constantinides. 343-350 [doi]
- A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature DescriptorsMurad Qasaimeh, Joseph Zambreno, Phillip H. Jones. 351-354 [doi]
- Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-ChipTobias Alonso, Mario Ruiz, Angel Lopez Garcia-Arias, Gustavo Sutter, Jorge E. López de Vergara. 355-359 [doi]
- Latency Insensitive Design Styles for FPGAsMustafa Abbas, Vaughn Betz. 360-367 [doi]
- A Flexible K-Means Operator for Hybrid DatabasesZhenhao He, David Sidler, Zsolt István, Gustavo Alonso. 368-371 [doi]
- Lynq: A Lightweight Software Layer for Rapid SoC FPGA PrototypingJonathan Déchelotte, Russell Tessier, Dominique Dallet, Jérémie Crenne. 372-375 [doi]
- Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous ChipsSam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José Núñez-Yáñez. 376-380 [doi]
- f-CNNx: A Toolflow for Mapping Multiple Convolutional Neural Networks on FPGAsStylianos I. Venieris, Christos-Savvas Bouganis. 381-388 [doi]
- CRRS: Custom Regression and Regularisation Solver for Large-Scale Linear SystemsAndreea-Ingrid Cross, Liucheng Guo, Wayne Luk, Mark Salmon. 389-393 [doi]
- A Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Work and Weight Load BalancingTong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang, Rushi Patel, Martin C. Herbordt. 394-398 [doi]
- Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAsMário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto. 399-402 [doi]
- An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip DebugAl-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton. 403-410 [doi]
- DLA: Compiler and FPGA Overlay for Neural Network Inference AccelerationMohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu. 411-418 [doi]
- An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAsThiem Van Chu, Kenji Kise. 419-426 [doi]
- Machine-Learning Based Congestion Estimation for Modern FPGAsDani Maarouf, Abeer Alhyari, Ziad Abuowaimer, Timothy Martin, Andrew Gunter, Gary Gréwal, Shawki Areibi, Anthony Vannelli. 427-434 [doi]
- FPGASwarm: High Throughput Model Checking on FPGAsShenghsun Cho, Michael Ferdman, Peter Milder. 435-442 [doi]
- Lightweight Secure Processor Prototype on FPGAYao Liu 0006, Ray C. C. Cheung, Hei Wong. 443-444 [doi]
- An Application-Specific Field-Programmable Tree Ensemble ArchitectureJan Kühn, Yiannos Manoli. 445-446 [doi]
- Facilitating Easier Access to FPGAs in the Heterogeneous Cloud EcosystemsUmar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis. 447-448 [doi]
- Cycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial IntelligenceHabib ul Hasan Khan, Diana Göhringer. 449-450 [doi]
- A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability TradeoffsBehzad Salami 0001, Osman S. Ünsal, Adrián Cristal. 451-452 [doi]
- Digital Pre-distortion Implemented Using FPGADeclan Byrne, Ronan Farrell, Sidath Madhuwantha, Miriam Leeser, John Dooley. 453-454 [doi]
- Accelerated Wire-Speed Packet Capture at 200 GbpsLukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek. 455-456 [doi]
- A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2)Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato. 457-458 [doi]
- viciLogic2.0 Online Learning and Prototyping Using PYNQFearghal Morgan, Declan O'Loughlin, Jeremy Audiger, Yohan Boyer, Frank Callaly. 459-460 [doi]
- Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUsMasayuki Shimoda, Shimpei Sato, Hiroki Nakahara. 461-462 [doi]
- Towards in the Field Fast Pathogens Detection Using FPGAsSimone Casale Brunet, Thierry Schüpbach, Nicolas Guex, Christian Iseli, Alan Bridge, Dmitry Kuznetsov, Christian J. A. Sigrist, Phillippe Lemercier, Ioannis Xenarios, Endri Bezati. 463-464 [doi]
- ADAS and Video Surveillance Analytics System Using Deep Learning Algorithms on FPGAYi Shan. 465-466 [doi]