Table of Contents

• Exploring the potential of reconfigurable platforms for order book updateConghui He, Haohuan Fu, Wayne Luk, Weijia Li, Guangen Yang. 1-8 [doi]
• One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAsGaël Deest, Tomofumi Yuki, Sanjay Rajopadhye, Steven Derrien. 1-8 [doi]
• A programming model and runtime system for approximation-aware heterogeneous computingIoannis Parnassos, Nikolaos Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Athanasios Gkaras, Konstantinos Kanellis, Christos D. Antonopoulos, Michalis Spyrou, Manolis Maroudas. 1-4 [doi]
• A fully connected layer elimination for a binarizec convolutional neural network on an FPGAHiroki Nakahara, Tomoya Fujii, Shimpei Sato. 1-4 [doi]
• PolyPC: Polymorphic parallel computing framework on embedded reconfigurable systemHongyuan Ding, Miaoqing Huang. 1-8 [doi]
• Latency-driven design for FPGA-based convolutional neural networksStylianos I. Venieris, Christos-Savvas Bouganis. 1-8 [doi]
• An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networksYufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo. 1-8 [doi]
• The Monte Carlo PUFVladimir Rozic, Bohan Yang 0001, Jo Vliegen, Nele Mentens, Ingrid Verbauwhede. 1-6 [doi]
• On accelerating pair-HMM computations in programmable hardwareSubho S. Banerjee, Mohamed El-Hadedy, Ching Y. Tan, Zbigniew T. Kalbarczyk, Steven S. Lumetta, Ravishankar K. Iyer. 1-8 [doi]
• Complete activation scheme for FPGA-oriented IP cores design protectionBrice Colombier, Ugo Mureddu, Marek Laban, Oto Petura, Lilian Bossuet, Viktor Fischer. 1 [doi]
• F-C3D: FPGA-based 3-dimensional convolutional neural networkHongxiang Fan, Xinyu Niu, Qiang Liu, Wayne Luk. 1-4 [doi]
• Rapid implementation of a partially reconfigurable video system with PYNQBrad L. Hutchings, Michael J. Wirthlin. 1-8 [doi]
• "All programmable FPGA, providing hardware efficiency to software programmers"Ivo Bolsens. 1-3 [doi]
• Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summationsYohann Uguen, Florent de Dinechin, Steven Derrien. 1-8 [doi]
• A pythonic approach for rapid hardware prototyping and instrumentationJohn Clow, Georgios Tzimpragos, Deeksha Dangwal, Sammy Guo, Joseph McMahan, Timothy Sherwood. 1-7 [doi]
• Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAsThomas B. Preuser. 1-7 [doi]
• A systematic approach to design and optimise streaming applications on FPGA using high-level synthesisMohammad Hosseinabady, Jose Luis Nunez-Yanez. 1-4 [doi]
• FISH: Linux system calls for FPGA acceleratorsKevin Nam, Blair Fort, Stephen Dean Brown. 1-4 [doi]
• Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platformsMuhsen Owaida, Hantian Zhang, Ce Zhang, Gustavo Alonso. 1-8 [doi]
• Deploying FPGAs to future-proof genome-wide analyses based on linkage disequilibriumDimitrios Bozikas, Nikolaos Alachiotis, Pavlos Pavlidis, Euripides Sotiriades, Apostolos Dollas. 1-8 [doi]
• VineTalk: Simplifying software access and sharing of FPGAs in datacentersStelios Mavridis, Emmanouil Pavlidakis, Ioannis Stamoulias, Christos Kozanitis, Nikolaos Chrysos, Christoforos Kachris, Dimitrios Soudris, Angelos Bilas. 1-4 [doi]
• Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devicesStephan Nolting, Lin Liu, Guillermo Payá Vayá. 1-4 [doi]
• High-quality view interpolation based on depth maps and its hardware implementationYanzhe Li, Kai Huang, Luc Claesen. 1-6 [doi]
• Dynamic power estimation based on switching activity propagationY. Nasser, Jean-Christophe Prévotet, M. Heiard, Jordane Lorandel. 1-2 [doi]
• A dynamic partial reconfigurable overlay concept for PYNQBenedikt Janßen, Pascal Zimprich, Michael Hübner. 1-4 [doi]
• Relocation-aware communication network for circuits on Xilinx FPGAsAdewale Adetomi, Godwin Enemali, Tughrul Arslan. 1-7 [doi]
• Parallel FPGA routing: Survey and challengesMirjana Stojilovic. 1-8 [doi]
• A partial reconfiguration based microphone array network emulatorBruno da Silva, Federico Domínguez, An Braeken, Abdellah Touhafi. 1-4 [doi]
• Decision tree based hardware power monitoring for run time dynamic power management in FPGAZhe Lin, Wei Zhang 0012, Sharad Sinha. 1-8 [doi]
• Optimizing streaming stencil time-step designs via FPGA floorplanningMarco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio. 1-4 [doi]
• Accelerating low bit-width convolutional neural networks with embedded FPGALi Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang. 1-4 [doi]
• An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimizationHenry Block, Tsutomu Maruyama. 1-8 [doi]
• FPGA acceleration of spark applications in a Pynq clusterChristoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris. 1 [doi]
• Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisationGengting Liu, Jim D. Garside, Steve Furber, Luis A. Plana, Dirk Koch. 1-8 [doi]
• Versatile deployment of FPGA accelerators in disaggregated data centers: A bioinformatics case studyNikolaos Alachiotis, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos. 1-4 [doi]
• ARMHEx: A framework for efficient DIFT in real-world SoCsMuhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat. 1 [doi]
• Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unitJose Raul Garcia Ordaz, Dirk Koch. 1-4 [doi]
• DFiant: A dataflow hardware description languageOron Port, Yoav Etsion. 1-4 [doi]
• Deflection-routed butterfly fat trees on FPGAsNachiket Kapre. 1-8 [doi]
• In-switch approximate processing: Delayed tasks management for MapReduce applicationsKoya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani. 1-4 [doi]
• Parallel RRT∗ architecture design for motion planningSize Xiao, Neil Bergmann, Adam Postula. 1-4 [doi]
• Application-specific soft-core vector processor for advanced driver assistance systemsStephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá Vayá. 1-2 [doi]
• Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of effortsHo-Cheung Ng, Shuanglong Liu, Wayne Luk. 1-8 [doi]
• Area-optimized montgomery multiplication on IGLOO 2 FPGAsPedro Maat C. Massolino, Lejla Batina, Ricardo Chaves, Nele Mentens. 1-4 [doi]
• Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGAChiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano. 1-4 [doi]
• FPGA acceleration of multilevel ORB feature extraction for computer visionJosh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond. 1-8 [doi]
• Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final additionJinnan Ding, Shuguo Li. 1-4 [doi]
• Heterogeneous virtualized network function framework for the data centerNaif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow. 1-8 [doi]
• A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERNR. Aggleton, L. Ardila-Perez, F. A. Ball, M. N. Balzer, J. Brooke, L. Calligaris, M. Caselle, D. Cieri, E. J. Clement, G. Hall, K. Harder, P. R. Hobson, G. M. Iles, T. James, K. Manolopoulos, T. Matsushita, A. D. Morton, D. Newbold, S. Paramesvaran, M. Pesaresi, I. D. Reid, A. W. Rose, Oliver Sander, T. Schuh, C. Shepherd-Themistocleous, A. Shtipliyski, S. P. Summers, A. Tapper, I. Tomalin, K. Uchida, P. Vichoudis, M. Weber. 1-4 [doi]
• Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBenchYingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello. 1-4 [doi]
• OpenSoC system architect: An open toolkit for building soft-cores on FPGAsFarzad Fatollahi-Fard, David Donofrio, John Shalf, John D. Leidel, Xi Wang, Yong Chen. 1 [doi]
• Body bias optimization for variable pipelined CGRATakuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano. 1-4 [doi]
• STRIPE: Signal selection for runtime power estimationJames J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides. 1-8 [doi]
• A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAsAlexander Wild, Georg T. Becker, Tim Güneysu. 1-7 [doi]
• A generic high throughput architecture for stream processingChristos Rousopoulos, Ektoras Karandeinos, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos. 1-5 [doi]
• FPGA-based design of a self-checking TMR voterUmar Afzaal, Jeong-A. Lee. 1-4 [doi]
• Toward a pixel-parallel architecture for graph cuts inference on FPGATianqi Gao, Jungwook Choi, Shang-Nien Tsai, Rob A. Rutenbar. 1-4 [doi]
• K-means clustering on CGRAJoão D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias. 1-4 [doi]
• Validating optimisations for chaotic simulationsJames Stanley Targett, Peter D. Düben, Wayne Luk. 1-4 [doi]
• Find the real speed limit: FPGA CAD for chip-specific application delay measurementIbrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz. 1-8 [doi]
• High performance binary neural networks on the Xeon+FPGA™ platformDuncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong. 1-4 [doi]
• Voltage drop-based fault attacks on FPGAs using valid bitstreamsDennis R. E. Gnad, Fabian Oboril, Mehdi Baradaran Tahoori. 1-7 [doi]
• Accelerated analysis of Boolean gene regulatory networksMitra Purandare, Raphael Polig, Christoph Hagleitner. 1-6 [doi]
• Flexible FPGA design for FDTD using OpenCLTobias Kenter, Jens Förstner, Christian Plessl. 1-7 [doi]
• Automated generation of banked memory architectures in the high-level synthesis of multi-threaded softwareYu-Ting Chen, Jason Helge Anderson. 1-8 [doi]
• Evaluating high-level design strategies on FPGAs for high-performance computingArtur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka. 1-4 [doi]
• Enabling partial reconfiguration and low latency routing using segmented FPGA NoCsKizhepatt Vipin, Jan Gray, Nachiket Kapre. 1-8 [doi]
• Tile size selection for optimized memory reuse in high-level synthesisJunyi Liu, John Wickerson, George A. Constantinides. 1-8 [doi]
• Demonstration of a partial reconfiguration based microphone array network emulatorBruno da Silva, Federico Domínguez, An Braeken, Abdellah Touhafi. 1 [doi]
• An implementation method of poisson image editing on FPGARyouhei Maeda, Tsutomu Maruyama. 1-6 [doi]
• High-performance video content recognition with long-term recurrent convolutional network for FPGAXiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen. 1-4 [doi]
• Phase calibrated ring oscillator PUF design and implementation on FPGAsWei Yan, Chenglu Jin, Fatemeh Tehranipoor, John A. Chandy. 1-8 [doi]
• FPGA acceleration of the scoring process of X!TANDEM for protein identificationJin Qiu, Ping Kang, Li Ding, Yipeng Yuan, Wenbo Yin, Lingli Wang. 1-4 [doi]
• Leveraging FVT-margins in design space exploration for FFGA-based CNN acceleratorsWeina Lu, Wenyan Lu, Jing Ye, Yu Hu, Xiaowei Li 0001. 1-4 [doi]
• doppioDB: A hardware accelerated databaseDavid Sidler, Muhsen Owaida, Zsolt István, Kaan Kara, Gustavo Alonso. 1 [doi]
• Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworksJulian Caba, Fernando Rincoon, Julio Dondo Gazzano. 1-2 [doi]
• Customised pearlmutter propagation: A hardware architecture for trust region policy optimisationShengjia Shao, Wayne Luk. 1-6 [doi]
• Reliable SEU monitoring and recovery using a programmable configuration controllerLingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel. 1-6 [doi]
• Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUsLester Kalms, Diana Göhringer. 1-4 [doi]
• HPC on FPGA clouds: 3D FFTs and implications for molecular dynamicsJiayi Sheng, Chen Yang, Ahmed Sanaullah, Michael Papamichael, Adrian M. Caulfield, Martin C. Herbordt. 1-4 [doi]
• Shielding non-trusted IPs in SoCsFestus Hategekimana, Taylor J. L. Whitaker, Md Jubaer Hossain Pantho, Christophe Bobda. 1-4 [doi]
• A high-throughput reconfigurable processing array for neural networksEphrem Wu, Xiaoqian Zhang, David Berman, Inkeun Cho. 1-4 [doi]
• A high-performance system-on-chip architecture for direct tracking for SLAMKonstantinos Boikos, Christos-Savvas Bouganis. 1-7 [doi]
• FPGA modeling techniques for detecting and demodulating multiple wireless protocolsBenjamin Drozdenko, Suranga Handagala, Kaushik R. Chowdhury, Miriam Leeser. 1-4 [doi]
• FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objectsAoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai. 1 [doi]
• Parallel dot-products for deep learning on FPGAMário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto. 1-4 [doi]
• Evaluating FPGA clusters under wide ranges of design parametersGrace Zgheib, Paolo Ienne. 1-8 [doi]
• Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniquesPavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton. 1-4 [doi]
• Broken-Karatsuba multiplication and its application to Montgomery modular multiplicationJinnan Ding, Shuguo Li. 1-4 [doi]
• High throughput AES encryption/decryption with efficient reordering and merging techniquesLijuan Li, Shuguo Li. 1-4 [doi]
• Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demoDavid J. Greaves. 1 [doi]
• An implementation of list successive cancellation decoder with large list size for polar codesChenyang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui, ChongYang Zeng, Jie Jin, Bin Li. 1-4 [doi]
• In-network online data analytics with FPGAsRyan Cooke, Suhaib A. Fahmy. 1-2 [doi]
• PAAS: A system level simulator for heterogeneous computing architecturesTingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang 0012. 1-8 [doi]
• A security library for FPGA interlaysAnuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch. 1-4 [doi]
• Learning-based interconnect-aware dataflow accelerator optimizationShuangnan Liu, Benjamin Carrión Schäfer. 1-7 [doi]
• Evaluating high-level design strategies on FPGAs for high-performance computingArtur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka. 1-4 [doi]
• REAPR: Reconfigurable engine for automata processingTed Xie, Vinh Dang, Jack Wadden, Kevin Skadron, Mircea Stan. 1-8 [doi]
• Scalable high-performance architecture for convolutional ternary neural networks on FPGAAdrien Prost-Boucle, Alban Bourge, Frédéric Pétrot, Hande Alemdar, Nicholas Caldwell, Vincent Leroy. 1-7 [doi]
• Quantifying and mitigating the costs of FPGA virtualizationSadegh Yazdanshenas, Vaughn Betz. 1-7 [doi]
• ARMHEx: A hardware extension for DIFT on ARM-based SoCsMuhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat. 1-7 [doi]
• Transparent memory encryption and authenticationMario Werner, Thomas Unterluggauer, Robert Schilling, David Schaffenrath, Stefan Mangard. 1-6 [doi]
• Vivado design interface: An export/import capability for Vivado FPGA designsThomas Townsend, Brent E. Nelson. 1-7 [doi]
• Mapping of P4 match action tables to FPGAMichal Kekely, Jan Korenek. 1-2 [doi]
• Dynamic bitwidth assignment for efficient dot productsSimon Joel Schmidt, David Boland. 1-8 [doi]
• Line rate programmable packet processing in 100Gb networksPavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely. 1 [doi]
• Comparison of hardware and software implementations of selected lightweight block ciphersWilliam Diehl, Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj. 1-4 [doi]
• Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairsYifeng Mo, Shuguo Li. 1-6 [doi]
• TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural featuresEric Matthews, Lesley Shannon. 1-4 [doi]
• A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGAHiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, M. Shimoda, Simpei Sato. 1 [doi]