Umar Afzaal - researchr alias

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Viewing Publication 1 - 9 from 9

2023

On the Evolutionary Synthesis of Fault-Resilient Digital CircuitsUmar Afzaal, Abdus Sami Hassan, Muhammad Usman, Jeong-A Lee. tec, 27(2):281-295, April 2023. [doi]

Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency PredictionByungHo Choi, Yonghwi Kwon 0002, Umar Afzaal, Youngsoo Shin. iscas 2023: 1-4 [doi]

2020

Low-cost Hardware Redundancy for Fault-mitigation in Power-constrained IoT SystemsUmar Afzaal, Jeong-A Lee. ictc 2020: 60-62 [doi]

Trading the Reliability of Approximate TMR in FPGAs with the Cost of MitigationUmar Afzaal, Jeong-A Lee. dsd 2020: 660-663 [doi]

Improved error detection performance of logic implication checking in FPGA circuitsUmar Afzaal, Abdus Sami Hassan, Jeong-A Lee. mam, 78:103179, 2020. [doi]

2019

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic UpdatesInayat Ullah, Zahid Ullah, Umar Afzaal, Jeong-A Lee. tvlsi, 27(6):1298-1307, 2019. [doi]

2018

Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication CheckingUmar Afzaal, Abdus Sami Hassan, Tooba Arifeen, Jeong-A Lee. dsd 2018: 196-200 [doi]

High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGAInayat Ullah, Umar Afzaal, Zahid Ullah, Jeong-A Lee. dsd 2018: 16-21 [doi]

2017

FPGA-based design of a self-checking TMR voterUmar Afzaal, Jeong-A. Lee. fpl 2017: 1-4 [doi]

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