Table of Contents

• MACO: A HW-Mapping Co-optimization Framework for DNN AcceleratorsWujie Zhong, Zijun Jiang, Yangdi Lyu. 1-7 [doi]
• KAPLA: Scalable NN Accelerator Dataflow Design Space Structuring and Fast ExploringZhiyao Li, Mingyu Gao 0001. 8-15 [doi]
• Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator PerformanceArya Fayyazi, Mehdi Kamal, Massoud Pedram. 16-22 [doi]
• A Computation and Energy Efficient Hardware Architecture for SSL AccelerationHuidong Ji, Sheng Li 0019, Yue Cao, Chen Ding, Jiawei Xu 0001, Qitao Tan, Jun Liu, Ao Li 0004, Xulong Tang, Lirong Zheng 0001, Geng Yuan, Zhuo Zou. 23-29 [doi]
• Sequential Printed Multilayer Perceptron Circuits for Super-TinyML Multi-Sensory ApplicationsGurol Saglam, Florentia Afentaki, Georgios Zervakis 0001, Mehdi B. Tahoori. 30-35 [doi]
• Learning to Prune and Low-Rank Adaptation for Compact Language Model DeploymentAsmer Hamid Ali, Fan Zhang 0069, Li Yang 0009, Deliang Fan. 36-42 [doi]
• LightCL: Compact Continual Learning with Low Memory Footprint For Edge DeviceZeqing Wang, Fei Cheng, Kangye Ji, Bohu Huang. 43-50 [doi]
• Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge DevicesHiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu. 51-57 [doi]
• High-Effort Logic Synthesis Using Randomized TransductionYukio Miyasaka, Alan Mishchenko, John Wawrzynek, Dino Ruic, Xiaoqing Xu. 58-64 [doi]
• PIRLLS: Pretraining with Imitation and RL Finetuning for Logic SynthesisGuande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi 0001, Kang Zhao. 65-71 [doi]
• MTLSO: A Multi-Task Learning Approach for Logic Synthesis OptimizationFaezeh Faez, Raika Karimi, Yingxue Zhang 0001, Xing Li, Lei Chen 0031, Mingxuan Yuan, Mahdi Biparva. 72-78 [doi]
• ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic AnalysisTsung-Yu Liu, Yen An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng. 79-85 [doi]
• High-Parallel In-Memory NTT Engine with Hierarchical Structure and Even-Odd Data MappingBing Li 0017, Huaijun Liu, Yibo Du, Ying Wang 0001. 86-92 [doi]
• Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot LearningHao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu. 93-99 [doi]
• DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task LevelTianyi Yu, Tianyu Liao, Mufeng Zhou, Xiaotian Chu, Guodong Yin, Mingyen Lee, Yongpan Liu, Huazhong Yang, Xueqing Li. 100-105 [doi]
• Deep Learning Inspired Capacitance Extraction TechniquesWenjian Yu, Shan Shen, Dingcheng Yang, Haoyuan Li, Jiechen Huang, Chunyan Pei. 106-112 [doi]
• Enhanced Operator Learning for Scalable and Ultra-fast Thermal Simulation in 3D-IC DesignXinling Yu, Ziyue Liu 0003, Hai Li 0008, Ian A. Young, Zheng Zhang 0005. 113 [doi]
• Boosting the Performance of Transistor-Level Circuit Simulation with GNNJiqing Jiang, Yongqiang Duan, Zhou Jin 0001. 114-120 [doi]
• Emag-Aware ML-Based Layout Optimization for High-Speed IC DesignGarth Sundberg, Rodger Luo. 121-127 [doi]
• Invited paper: Bridging EDA and Silicon Photonics Design: Enabling Robust-by-Design Photonic Integrated CircuitsZahra Ghanaatian, Asif Mirza, Amin Shafiee, Sudeep Pasricha, Mahdi Nikdast. 128-134 [doi]
• Invited paper: SPICE-Compatible Modeling and Design for Electronic-Photonic Integrated CircuitsYuxiang Fu, Yinyi Liu, Ngai Wong, Jiang Xu 0001. 135-140 [doi]
• Invited paper: Modeling and Simulation of Silicon Photonics Systems in SystemVerilog/XMODELJaeha Kim. 141-146 [doi]
• Invited paper: Si Photonic Ring-Resonator-Based WDM TransceiversWoo-Young Choi, Dae-Won Rho, Jae-Koo Park, Seung-Jae Yang, Jae-Ho Lee, Yongjin Ji. 147 [doi]
• ViDA: Video Diffusion Transformer Acceleration with Differential Approximation and Adaptive DataflowLi Ding 0012, Jun Liu 0071, Shan Huang, Guohao Dai. 148-154 [doi]
• APTO: Accelerating Serialization-Based Point Cloud Transformers with Position-Aware PruningQichu Sun, Rui Meng, Haishuang Fan, Fangqiang Ding, Linxi Lu, Jingya Wu, Xiaowei Li 0001, Guihai Yan. 155-162 [doi]
• UEDA: A Universal And Efficient Deformable Attention Accelerator For Various Vision TasksKairui Sun, Meiqi Wang, Junhai Zhou, Zhongfeng Wang 0001. 163-169 [doi]
• Deploying Diffusion Models with Scheduling Space Search and Memory Overflow Prevention Based on Graph OptimizationHao Zhou, Yang Liu, Hongji Wang, Enhao Tang, Shun Li, Yifan Zhang, Guohao Dai, Yongpan Liu, Kun Wang 0005. 170-176 [doi]
• TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device DeploymentGuang Yang, Xinming Yan, Hui Kou, Zihan Zou, Qingwen Wei, Hao Cai 0001, Bo Liu 0019. 177-182 [doi]
• A Practical Randomized GMRES Algorithm for Solving Linear Equation System in Circuit SimulationBaiyu Chen, Jiawen Cheng, Wenjian Yu. 183-189 [doi]
• Balancing Objective Optimization and Constraint Satisfaction for Robust Analog Circuit OptimizationJintao Li, Haochang Zhi, Jiang Xiao, Yanhan Zeng, Weiwei Shan, Yun Li 0002. 190-196 [doi]
• Analog Circuit Transfer Method Across Technology Nodes via Transistor BehaviorHaochang Zhi, Jintao Li, Yun Li 0002, Weiwei Shan. 197-203 [doi]
• AIPlace: Analog IC Placement with Multi-Task Learning FrameworkLijie Wang, Jing Wang, Song Chen 0001, Qi Xu. 204-210 [doi]
• Stochastic Multivariate Universal-Radix Finite-State Machine: a Theoretically and Practically Elegant Nonlinear Function ApproximatorXincheng Feng, Guodong Shen, JianHao Hu, Meng Li 0016, Ngai Wong. 211-217 [doi]
• ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point MultiplierZhongyu Guan, Qiang Liu 0011, Guangdong Lin. 218-223 [doi]
• AmPEC: Approximate MRAM with Partial Error Correction for Fine-grained Energy-quality Trade-offLan-yang Sun, Yaoru Hou, Hao Cai 0001. 224-229 [doi]
• HyPPO: Hybrid Piece-wise Polynomial Approximation and Optimization for Hardware Efficient DesignsLakshmi Sai Niharika Vulchi, Pranathi Valipireddy, Mahati Basavaraju, Madhav Rao. 230-236 [doi]
• Hybrid Temporal Computing for Lower Power Hardware AcceleratorsMaliha Tasnim, Sachin Sachdeva, Yibo Liu, Sheldon X.-D. Tan. 237-244 [doi]
• PULSE: Progressive Utilization of Log-Structured Techniques to Ease SSD Write Amplification in B-epsilon-treeHuai-De Peng, Yi-Shen Chen, Tseng-Yi Chen, Yuan-Hao Chang 0001. 245-250 [doi]
• Rethinking B-epsilon tree Indexing Structure over NVM with the Support of Multi-write ModesHui-Tang Luo, Tseng-Yi Chen. 251-257 [doi]
• End-to-end Compilation is All FPGAs Need: A Unified Overlay-based FPGA Compiler for Deep LearningKai Qian, Haodong Lu 0001, Yinqiu Liu, Zexu Zhang, Kun Wang 0005. 258-264 [doi]
• HDCC: A Hierarchical Dataflow-Oriented CGRA Compiler for Complex ApplicationsShangli Li, Mingjie Xing, Yanjun Wu. 265-271 [doi]
• HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAsQilin Si, Benjamin Carrión Schäfer. 272-278 [doi]
• Fast Routing Algorithm for Mask Stitching Region of Ultra Large Wafer Scale IntegrationZhen Zhuang, Quan Chen 0007, Hao Yu 0001, Tsung-Yi Ho. 279-284 [doi]
• The Survey of 2.5D Integrated Architecture: An EDA perspectiveShixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu 0001. 285-293 [doi]
• Toward Advancing 3D-ICs Physical Design: Challenges and OpportunitiesXueyan Zhao, Weiguo Li, Zhisheng Zeng, Zhipeng Huang 0009, Biwei Xie, Xingquan Li, Yungang Bao. 294-301 [doi]
• Processing-Near-Memory with Chip Level 3D-ICMiao Liu, Qingqing Sun, David Wei Zhang. 302-307 [doi]
• Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICsGyumin Kim, Heechun Park. 308-314 [doi]
• A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia DetectionYifan Qin, Zhenge Jia, Zheyu Yan, Jay Mok, Manto Yung, Yu Liu 0007, Xuejiao Liu, Wujie Wen, Luhong Liang, Kwang-Ting Tim Cheng, Xiaobo Sharon Hu, Yiyu Shi 0001. 315-316 [doi]
• Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR ApplicationsZhiwei Zhong, Yijie Wei, Lance Christopher Go, Yiqi Li, Jie Gu 0001. 317-320 [doi]
• Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse KinematicsQiankai Cao, Yiqi Li, Juin Chuen Oh, Jie Gu 0001. 321-324 [doi]
• A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN ProcessorYuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge. 325-327 [doi]
• Learned Image Codec on FPGA: Algorithm, Architecture and System DesignHeming Sun, Jing Wang, Silu Liu, Shinji Kimura, Masahiro Fujita. 328-331 [doi]
• Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge DevicesNaoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi. 332-334 [doi]
• A High-Density Hybrid Buck Converter with a Charge Converging Phase Reducing Inductor Current for 12V Power Supply SystemsYichao Ji, Ji Jin, Lin Cheng 0001. 335-337 [doi]
• A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET TechnologyYunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han. 338-341 [doi]
• A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data RateYi Zhang 0092, Minzhe Tang, Zheng Li 0021, Dongfan Xu, Kazuaki Kunihiro, Hiroyuki Sakai 0009, Atsushi Shirane, Kenichi Okada 0001. 342-343 [doi]
• Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave DetectionYuyang Zhu, Zunsong Yang, Zhenyu Cheng 0003, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka. 344-347 [doi]
• Self-recovery hysteresis control based on-chip SC DC-DC converter robust to load fluctuationKoji Kikuta, Takashi Hisakado, Mahfuzul Islam 0001. 348-351 [doi]
• A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NRDongfan Xu, Minzhe Tang, Yi Zhang 0092, Zheng Li 0021, Jian Pang, Atsushi Shirane, Kenichi Okada 0001. 352-353 [doi]
• A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMOChenxin Liu, Zheng Li 0021, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Shinsuke Hara, Akifumi Kasamatsu, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada 0001. 354-355 [doi]
• Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devicesKenji Mii, Daisuke Kanemoto, Tetsuya Hirose. 356-359 [doi]
• Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space ProbesSota Kano, Naoto Usami, Atsushi Tomiki, Tetsuya Iizuka. 360-363 [doi]
• Design of 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-RecordingHiroaki Kitaike, Hironori Tagawa, Shufan Xu, Ruilin Zhang, Kunyang Liu, Kiichi Niitsu. 364-367 [doi]
• Ultra Low-power Capacitively-coupled Chopper Amplifier Focusing on the Sparsity of Compressed Sensing for EEG RecordingKenji Mii, Daisuke Kanemoto, Tetsuya Hirose. 368-371 [doi]
• Standard Cell Layout Generation: Review, Challenges, and Future WorksChung-Kuan Cheng, Byeonggon Kang, Bill Lin 0001, Yucheng Wang. 372-378 [doi]
• ML-assisted SRAM Soft Error Rate Characterization: Opportunities and ChallengesMasanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi. 379-384 [doi]
• Invited Paper: Boosting Standard Cell Library Characterization with Machine LearningZhengrui Chen, Chengjun Guo, Zixuan Song, GuoZhu Feng, Shizhang Wang, Li Zhang 0021, Xunzhao Yin, Zhenhua Wu, Zheyu Yan, Cheng Zhuo. 385-391 [doi]
• Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard CellsKairong Guo, Xiaohan Gao, Haoyi Zhang, Runsheng Wang, Ru Huang 0001, Yibo Lin. 392 [doi]
• Graph-Based Timing Prediction at Early-Stage RTL Using Large Language ModelFahad Rahman Amik, Yousef Safari, Zhanguang Zhang, Boris Vaisband. 393-400 [doi]
• SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner ConsiderationYushan Wang, Xu He, Renjun Zhao, Yao Wang 0002, Chang Liu 0019, Yang Guo 0002. 401-406 [doi]
• iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing AnalysisBoyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang. 407-415 [doi]
• PathGen: An Efficient Parallel Critical Path Generation AlgorithmChe Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang. 416-424 [doi]
• Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value DistributionKaixiang Zhu, Wai-Shing Luk, Lingli Wang. 425-432 [doi]
• Making Legacy Hardware Robust against Side Channel Attacks via High-Level SynthesisMd. Imtiaz Rashid, Benjamin Carrión Schäfer. 433-439 [doi]
• Machine Learning-Based Real-Time Detection of Power Analysis Attacks Using Supply Voltage ComparisonsNan Wang 0003, Ruichao Liu, Yufeng Shan, Yu Zhu 0005, Song Chen 0001. 440-446 [doi]
• Side-channel Collision Attacks on Hyper-Dimensional Computing based on Emerging Resistive MemoriesBrojogopal Sapui, Mehdi B. Tahoori. 447-453 [doi]
• Dep-TEE: Decoupled Memory Protection for Secure and Scalable Inter-enclave Communication on RISC-VShangjie Pan, Xuanyao Peng, Zeyuan Man, Xiquan Zhao, Dongrong Zhang, Bicheng Yang, Dong Du 0003, Hang Lu, Yubin Xia, Xiaowei Li 0001. 454-460 [doi]
• Through Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC SystemsHassan Nassar, Jeferson González-Gómez, Varun Manjunath, Lars Bauer, Jörg Henkel. 461-467 [doi]
• Theoretical Optimal Specifications of Memcapacitors for Charge-Based In-Memory ComputingZichen Qian, Rentao Wan, Chin-Hsiang Liao, Steven Koester, Mingoo Seok. 468-475 [doi]
• An Island Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided LogicUmar Afzaal, Seunggyu Lee, Youngsoo Shin. 476-482 [doi]
• PIMutation: Exploring the Potential of Real PIM Architecture for Quantum Circuit SimulationDongin Lee, Enhyeok Jang, Seungwoo Choi, Junwoong An, Cheolhwan Kim, Won Woo Ro. 483-490 [doi]
• A Fail-Slow Detection Framework for HBM DevicesZikang Xu, Yiming Zhang 0003, Zhirong Shen. 491-497 [doi]
• DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled RepresentationsSadaf Khan, Zhengyuan Shi, Ziyang Zheng, Min Li 0019, Qiang Xu 0001. 498-504 [doi]
• A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design TasksWenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie. 505-512 [doi]
• ParaFormer: A Hybrid Graph Neural Network and Transformer Approach for Pre-Routing Parasitic RC PredictionJongho Yoon, Jakang Lee, Donggyu Kim, Junseok Hur, Seokhyeong Kang. 513-519 [doi]
• Static IR Drop Prediction with Limited Data from Real DesignsLizi Zhang, Azadeh Davoodi. 520-526 [doi]
• Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL StageShang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie. 527-533 [doi]
• Accelerator for LLM-Enhanced GNN with Product Quantization and Unified IndexingJiaming Xu, Jinhao Li 0006, Jun Liu 0071, Hao Zhou, Guohao Dai. 534-540 [doi]
• MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI AcceleratorCong Wang, Zeming Chen, Shanshi Huang. 541-547 [doi]
• DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable ArchitecturesHaojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin. 548-553 [doi]
• MPICC: Multiple-Precision Inter-Combined MAC Unit with Stochastic Rounding for Ultra-Low-Precision TrainingLeran Huang, Yongpan Liu, Xinyuan Lin, Chenhan Wei, Wenyu Sun, Zengwei Wang, Boran Cao, Chi Zhang, Xiaoxia Fu, Wentao Zhao, Sheng Zhang. 554-559 [doi]
• Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based ModelsWei-Yao Kao, Tai-Jung Lin, Yao-Wen Chang. 560-566 [doi]
• Zipper: Latency-Tolerant Optimizations for High-Performance BusesShibo Chen, Hailun Zhang, Todd M. Austin. 567-574 [doi]
• A Buffer Reservation Scheduling Strategy for Enhancing Performance of NoC Router BypassingZixuan Liu, Yaoyao Ye. 575-580 [doi]
• RUNoC: Re-inject into the Underground Network to Alleviate Congestion in Large-Scale NoCXinghao Zhu, Jiyuan Bai, Zifeng Zhao, Qirong Yu, Xiaofang Zhou, Gengsheng Chen. 581-586 [doi]
• A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband ProcessingLimin Jiang, Yi Shi 0004, Yintao Liu, Qingyu Deng, Siyi Xu, Yihao Shen, Fangfang Ye, Shan Cao, Zhiyuan Jiang. 587-593 [doi]
• Exploiting Differential-Based Data Encoding for Enhanced Query EfficiencyFangxin Liu, Zongwu Wang, Peng Xu, Shiyuan Huang, Li Jiang 0002. 594-600 [doi]
• Automated Power-saving User-interfaces for Application DesignersHuan-Chun Yeh, Yu-Zheng Su, Chun-Han Lin. 601-606 [doi]
• An Edge AI and Adaptive Embedded System Design for Agricultural Robotics ApplicationsChun-Hsian Huang, Zhi-Rui Chen, Huai-Shu Hsu. 607-613 [doi]
• AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMsZhiyuan Yan 0003, Wenji Fang, Mengming Li, Min Li 0019, Shang Liu, Zhiyao Xie, Hongce Zhang. 614-621 [doi]
• Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural NetworksThai-Hoang Nguyen, Youngjin Ju, Dongsub Yoon, Hyojin Choi. 622-627 [doi]
• Efficient ML-Based Transient Thermal Prediction for 3D-ICsYun-Feng Yang, Wei-Shen Wang, Yung-Jen Lee, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying Shiun Li, Jessica Yen, Lang Lin. 628-634 [doi]
• Device-Aware Test for Anomalous Charge Trapping in FeFETsSicong Yuan, Changhao Wang, Moritz Fieback, Hanzhi Xun, Mottaqiallah Taouil, Xiuyan Li, Danyang Chen, Lin Wang, Nicolò Bellarmino, Riccardo Cantoro, Said Hamdioui. 635-641 [doi]
• 3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory MacroYiming Chen, Xirui Du, Guodong Yin, Wenjun Tang, Yongpan Liu, Huazhong Yang, Xueqing Li. 642-647 [doi]
• HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning WorkloadsShubham Negi, Utkarsh Saxena, Deepika Sharma, Kaushik Roy 0001. 648-655 [doi]
• MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory ProcessingLiyan Chen, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao, Naifeng Jing. 656-662 [doi]
• A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation StrategiesYitong Zhou, Wente Yi, Sifan Sun, Wenjia Wang, Jinyu Bai, He Zhang 0011, Wang Kang 0001. 663-668 [doi]
• Use Cases and Deployment of ML in IC Physical DesignAmur Ghose, Andrew B. Kahng, Sayak Kundu, Yiting Liu, Bodhisatta Pramanik, Zhiang Wang, Dooseok Yoon. 669-675 [doi]
• Leveraging Machine Learning Techniques for Traditional EDA Workflow EnhancementJinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, SeongHyeon Park, Jaemin Seo, Jongho Yoon, Seokhyeong Kang. 676-682 [doi]
• ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDAHyunsu Chae, Song Hang Chai, Taiyun Chi, Sensen Li, David Z. Pan. 683-689 [doi]
• ML for Computational Lithography: Practical RecipesYoungsoo Shin. 690-692 [doi]
• Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge InferenceWei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu. 693-699 [doi]
• SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge DeviceXilong Kang, Qingwen Wei, Ningyuan Li 0004, Xingyu Xu 0008, Hao Cai 0001, Bo Liu 0019. 700-705 [doi]
• FactorFlow: Mapping GEMMs on Spatial Architectures through Adaptive Programming and Greedy OptimizationMarco Ronzani, Cristina Silvano. 706-712 [doi]
• LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network InferenceYanyue Xie, Zhengang Li, Dana Diaconu, Suranga Handagala, Miriam Leeser, Xue Lin 0001. 713-719 [doi]
• A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNsHaoxiang Zhou, Zikun Wei, Dingbang Liu, Liuyang Zhang, Chenchen Ding, Jiaqi Yang, Wei Mao 0002, Hao Yu 0001. 720-726 [doi]
• HyCOMP: A Compiler for ANN-SNN Hybrid AcceleratorsYitian Zhou, Yue Li, Yang Hong. 727-733 [doi]
• NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural NetworksHaomin Li, Fangxin Liu, Zewen Sun, Zongwu Wang, Shiyuan Huang, Ning Yang, Li Jiang 0002. 734-740 [doi]
• SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural NetworksBo Li, Yue Liu, Wei Liu 0118, Jinghai Wang, Xiao Huang, Zhiyi Yu, Shanlin Xiao. 741-747 [doi]
• OpticalHDC: Ultra-fast Photonic Hyperdimensional Computing AcceleratorJiaqi Liu, Yiwen Ma. 748-753 [doi]
• Design and In-training Optimization of Binary Search ADC for Flexible ClassifiersPaula Carolina Lozano Duarte, Florentia Afentaki, Georgios Zervakis 0001, Mehdi B. Tahoori. 754-760 [doi]
• Paired-Spacing-Constrained Package Routing with Net Ordering OptimizationYi-Sian Ciou, Ying-Jie Jiang, Yi-Yu Liu, Shao-Yun Fang, Wen-Hao Liu 0001. 761-767 [doi]
• Hybrid Detour Refinement Strategy for Package Substrate RoutingDing-Hsun Lin, Tsubasa Koyama, Yu-Jen Chen, Keng-Tuan Chang, Chih-Yi Huang, Chen-Chao Wang, Tsung-Yi Ho. 768-773 [doi]
• On Awareness of Offset-Via and Teardrop in Advanced Packaging Interconnect SynthesisHao-Ju Chang, Yu-Hung Chen, Hao-Wei Huang, Yihua Yeh, Hung-Ming Chen, Chien-Nan Jimmy Liu. 774-780 [doi]
• PCBAgent: An Agent-based Framework for High-Density Printed Circuit Board PlacementLin Chen, Ran Chen, Shoubo Hu, Xufeng Yao, Zhentao Tang, Shixiong Kai, Siyuan Xu, Mingxuan Yuan, Jianye Hao, Bei Yu 0001, Jiang Xu. 781-787 [doi]
• NoXLock: SiP Activation and Licensing through Obfuscated on-Chip Network and Fuzzy TrafficMd. Saad Ul Haque, Azim Uddin, Jingbo Zhou, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor. 788-793 [doi]
• K-Gate Lock: Multi-Key Logic Locking Using Input Encoding Against Oracle-Guided AttacksKevin Lopez, Amin Rezaei 0001. 794-800 [doi]
• A Hybrid Machine Learning and Numeric Optimization Approach to Analog Circuit DeobfuscationDipali Deepak Jain, Guangwei Zhao, Rajesh Kumar Datta, Kaveh Shamsi. 801-807 [doi]
• RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking FrameworkKun Wang, Kaiyan Chang, Mengdi Wang, Xingqi Zou, Haobo Xu, Yinhe Han 0001, Ying Wang 0001. 808-813 [doi]
• LIBMixer: An all-MLP Architecture for Cell Library Characterization towards Design Space OptimizationJaeseung Lee, Sunggyu Jang, Jakang Lee, Seokhyeong Kang. 814-820 [doi]
• DefectTrackNet: Efficient Root Cause Analysis of Wafer Defects in Semiconductor Manufacturing Using a Lightweight CNN-Transformer ArchitectureLichao Zeng, Zhouzhouzhou Mei, Zhongyu Shi, Yining Chen. 821-827 [doi]
• Hybrid Compact Modeling Strategy: A Fully-Automated and Accurate Compact Model with Physical ConsistencyJinyoung Choi, HyunJoon Jeong, Jeong-Taek Kong, Soyoung Kim. 828-834 [doi]
• CAR-Net: Solving Electrical Crosstalk Problem in Capacitive Sensing ArrayQinghang Zhao, Tao Li. 835-841 [doi]
• PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog CircuitsYoungchang Choi, Sejin Park 0001, Ho-Jin Lee, Kyongsu Lee, Jae-Yoon Sim, Seokhyeong Kang. 842-848 [doi]
• AI-Guided Codesign for Novel Computing ParadigmsSuma George Cardwell, J. Darby Smith, Karan Patel, Andrew Maicke, Jared Arzate, Samuel Liu, Jaesuk Kwon, Christopher Allemang, Douglas Cale Crowder, Shashank Misra, Frances S. Chance, Catherine D. Schuman, Jean Anne C. Incorvia, James Bradley Aimone. 849-856 [doi]
• Towards Design Optimization of Analog Compute SystemsSara Achour. 857-864 [doi]
• Nature-GL: A Revolutionary Learning Paradigm Unleashing Nature's Power in Real-World Spatial-Temporal Graph LearningChuan Liu 0001, Chunshu Wu, Ruibing Song, Yousu Chen, Ang Li 0006, Michael C. Huang 0001, Tony Tong Geng. 865-871 [doi]
• ChemComp: A Compilation Framework for Computing with Chemical Reaction NetworksNicolas Bohm Agostini, Connah Johnson, William Cannon, Antonino Tumeo. 872-878 [doi]
• PPA-Aware Tier Partitioning for 3D IC Placement with ILP FormulationEunsol Jeong, Taewhan Kim 0001, Heechun Park. 879-885 [doi]
• FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCsZirui Li, Kanglin Tian, Jianwang Zhai, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu 0001, Kang Zhao. 886-892 [doi]
• Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent OptimizationCheng-Yu Chiang, Yi-Hsien Chiang, Chao-Chi Lan, Yang Hsu, Che-Ming Chang, Shao-Chi Huang, Sheng-hua Wang, Yao-Wen Chang, Hung-Ming Chen. 893-899 [doi]
• ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast SimulatorXinfei Liu, Siting Liu 0002, Bei Yu 0001, Song Chen 0001, Qi Xu. 900-906 [doi]
• An MIP-based Force-directed Large Scale Placement Refinement AlgorithmZewen Li, Ke Tang, Lang Feng 0001, Zhongfeng Wang 0001. 907-913 [doi]
• 2S: A Hybrid Ising-Classical-Machines Data-Driven QUBO Solver MethodArmin Abdollahi, Mehdi Kamal, Massoud Pedram. 914-920 [doi]
• Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal SchedulingDaniel Bochen Tan, Wan-Hsuan Lin, Jason Cong. 921-929 [doi]
• Back-end-aware Fault-tolerant Quantum Oracle SynthesisMingfei Yu, Alessandro Tempia Calvino, Mathias Soeken, Giovanni De Micheli. 930-937 [doi]
• FEI: Fusion Processing of Sensing Energy and Information for Self-Sustainable Infrared Smart Vision SystemHaijin Su, Xin Hong, Maimaiti Nazhamaiti, Ce Zhang, Li Luo, Qi Wei 0001, Zheyu Liu, Wenjie Deng, Yongzhe Zhang, Fei Qiao. 938-944 [doi]
• WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth MemorySeoyoon Jang, Sangouk Jeon, Kwanghyun Shin, Dongkwon Lee, Hankyu Chi, Wookjin Shin, Changhyun Pyo, Jaeha Kim, Dongsuk Jeon. 945-951 [doi]
• Compact Interleaved Thermal Control for Improving Throughput and Reliability of Networks-on-ChipTong Cheng, Zirui Xu, Xinyi Li, Li Li 0003, Yuxiang Fu. 952-958 [doi]
• E-QUARTIC: Energy Efficient Edge Ensemble of Convolutional Neural Networks for Resource-Optimized LearningLe Zhang, Onat Güngör, Flavio Ponzina, Tajana Rosing. 959-965 [doi]
• Hardware Error Detection with In-Situ Monitoring of Control Flow-Related SpecificationsTomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto. 966-973 [doi]
• LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored AccelerationShan Huang, Jinhao Li 0006, Zhen Yu, Jiancai Ye, Jiaming Xu, Ningyi Xu, Guohao Dai. 974-980 [doi]
• OPL4GPT: An Application Space Exploration of Optimal Programming Language for Hardware Design by LLMKimia Tasnia, Sazadur Rahman. 981-987 [doi]
• Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and AnalysisJiahao Gai, Hao Chen, Zhican Wang, Hongyu Zhou, Wanru Zhao, Nicholas D. Lane, Hongxiang Fan. 988-994 [doi]
• MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMsManar Abdelatty, Jingxiao Ma, Sherief Reda. 995-1001 [doi]
• SimEval: Investigating the Similarity Obstacle in LLM-based Hardware Code GenerationMohammad Akyash, Hadi Mardani Kamali. 1002-1007 [doi]
• In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence AnalysisYou-Kai Zheng, Ming-Liang Wei, Hsiang-Yun Cheng, Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong, Po-Hao Tseng, Hsiang-Pang Li. 1008-1015 [doi]
• A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator SystemsAnkur Limaye, Nicolas Bohm Agostini, Claudio Barone, Vito Giovanni Castellana, Michele Fiorito, Fabrizio Ferrandi, Andres Marquez, Antonino Tumeo. 1016-1022 [doi]
• Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph ColoringYuan Dai, Xuchen Gao, Chen Shen, Bingbing Peng, Wenbo Yin, Wai-Shing Luk, Lingli Wang. 1023-1030 [doi]
• HyperG: Multilevel GPU-Accelerated k-way Hypergraph PartitionerWan-Luan Lee, Dian-Lun Lin, Cheng-Hsiang Chiu, Ulf Schlichtmann, Tsung-Wei Huang. 1031-1040 [doi]
• Exploring and Exploiting Runtime Reconfigurable Floating Point Precision in Scientific Computing: a Case Study for Solving PDEsCong Hao. 1041-1047 [doi]
• A Holistic FPGA Architecture Exploration Framework for Deep Learning AccelerationJiadong Zhu, Dongsheng Zuo, Yuzhe Ma. 1048-1054 [doi]
• OpenGeMM: A Highly-Efficient GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory CouplingXiaoling Yi, Ryan Antonio, Joren Dumoulin, Jiacong Sun, Josse Van Delm, Guilherme Pereira Paim, Marian Verhelst. 1055-1061 [doi]
• Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer OptimizationsQijun Zhang, Zhiyao Xie. 1062-1069 [doi]
• An Efficient General-Purpose Optical Accelerator for Neural NetworksSijie Fei, Amro Eldebiky, Grace Li Zhang, Bing Li 0005, Ulf Schlichtmann. 1070-1076 [doi]
• ADEPT-Z: Zero-Shot Automated Circuit Topology Search for Pareto-Optimal Photonic Tensor CoresZiyang Jiang, Pingchuan Ma 0012, Meng Zhang, Z. Rena Huang, Jiaqi Gu 0002. 1077-1083 [doi]
• Reuse and Blend: A Weight-Sharing Energy-Efficient Optical Neural NetworkBo Xu, Yuetong Fang, Shaoliang Yu, Renjing Xu. 1084-1090 [doi]
• PhotonGraph: High-performance Photonic Graph Processing AcceleratorJiaqi Liu, Xianbin Li. 1091-1096 [doi]
• An Algebraic Approach to Partial Synthesis of Arithmetic CircuitsBhavani Sampathkumar, Ritaja Das, Bailey Martin, Florian Enescu, Priyank Kalla. 1097-1103 [doi]
• Hardware Synthesizable Exceptions using ContinuationsPaul Teng, Christophe Dubach. 1104-1111 [doi]
• Area-Oriented Optimization After Standard-Cell MappingAndrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli. 1112-1119 [doi]
• ROBIN: A Novel Framework for Accelerating Robust Multi-Variant TrainingYan Wang, Xingbin Wang, Yulan Su, Sisi Zhang, Zechao Lin, Dan Meng, Rui Hou 0001. 1120-1125 [doi]
• Dual-branch cross-modal fusion with local-to-global learning for UAV object detectionBinyi Fang, Yixin Yang 0004, Jingjing Chang, Ziyang Gao, Hai-Bao Chen. 1126-1132 [doi]
• H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR ApplicationsYiwei Zhao, Jinhui Chen, Sai Qian Zhang, Syed Shakib Sarwar, Kleber Hugo Stangherlin, Jorge Tomás Gómez, Jae-sun Seo, Barbara De Salvo, Chiao Liu, Phillip B. Gibbons, Ziyun Li. 1133-1141 [doi]
• Raads: Rapidus's AI/ML based assisted design flow to reduce design period halvedKoki Tsurusaki. 1142 [doi]
• DMCO: A Strategy for Design-Manufacturing Co-optimizationMasaharu Kobayashi. 1143 [doi]
• Advanced Packaging Technology and Design Methodology for Next Generation ChipletsHideki Sasaki. 1144 [doi]
• FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power ModelingQijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie. 1145-1152 [doi]
• DISS: A Novel Data Invalidation Scheme for Swap-Data on Flash Storage SystemsDingcui Yu, Longfei Luo, Han Wang, Yina Lv, Liang Shi. 1153-1159 [doi]
• Response Range Optimization for Run-Time Requirement Enforcement on MPSoCsKhalil Esper, Stefan Wildermann, Jürgen Teich. 1160-1166 [doi]
• TL-CSE: Microarchitecture-Compiler Co-design Space Exploration via Transfer LearningZheng Wu, Jinyi Shen, Xuyang Zhao, Changxu Liu, Li Shang, Fan Yang 0001. 1167-1173 [doi]
• RISC-V Driven Orchestration of Vector Processing Units and eFlash Compute-in-Memory Arrays for Fast and Accurate Keyword SpottingGunil Kang, Dahoon Park, Hojin Lee, Sangwoo Jung, Jiyong Park, Jung Gyu Min, Youngjoo Lee, Jaeha Kung. 1174-1180 [doi]
• Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor CoresShaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang 0001. 1181-1187 [doi]
• Large-Scale AGV Routing Based on Multi-FPGA SQA AccelerationThinh NguyenQuang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki. 1188-1194 [doi]
• A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network InferencePol Puigdemont, Enrico Russo 0002, Axel Wassington, Abhijit Das 0002, Sergi Abadal, Maurizio Palesi. 1195-1201 [doi]
• FPBA: Flexible Percentile-Based Allocation for Multiple-Bits-Per-Cell RRAMJunfei Liu, Anson Kahng. 1202-1208 [doi]
• Mpache: Interaction Aware Multi-level Cache Bypassing on GPUsMengyue Xi, Tianyu Guo 0009, Xuanteng Huang, Zejia Lin 0001, Xianwei Zhang 0001. 1209-1215 [doi]
• A Novel Mixed-Signal Flash-based Finite Impulse Response (FFIR) Filter for IoT ApplicationsCheng-Yen Lee, Sunil P. Khatri, Ali Ghrayeb. 1216-1222 [doi]
• TRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-TreeXing Wang, Tianhui Jiao, Shaochen Li, Yuchen Ma, Zhican Zhang, Zhichao Liu, Xi Chen, Xin Si. 1223-1229 [doi]
• Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing AwarenessYichen Cai, Linyu Zhu, Xinfei Guo. 1230-1236 [doi]
• Pin Access-aware Multiple Via Pillar Co-Design for Routability OptimizationMan-Ling Hong, Ying-Jie Jiang, Shao-Yun Fang. 1237-1242 [doi]
• ResCap: Fast-yet-Accurate Capacitance Extraction for Standard Cell Design by Physics-Guided Machine LearningJiun-Cheng Tsai, Hsuan-Ming Huang, Wei-Min Hsu, Pei-Ting Lee, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, Charles H.-P. Wen. 1243-1250 [doi]
• CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-ChipYan-Ting Chen, Zhidan Zheng, Shao-Yun Fang, Tsun-Ming Tseng, Ulf Schlichtmann. 1251-1256 [doi]
• Hardware Trojan Detection by Fine-grained Power Domain PartitioningTakahiro Ishikawa, Kose Yokooji, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani, Jun Shiomi. 1257-1263 [doi]
• Cryo-HT: Hardware Trojan Activated at Cryogenic TemperaturesAyano Takaya, Ryuichi Nakajima, Jun Shiomi, Michihiro Shintani. 1264-1269 [doi]
• Current consumption model for more efficient side-channel tolerant design at FPGA design stageDaisuke Fujimoto, Yuichi Hayashi. 1270-1274 [doi]
• White-box logic obfuscation: A Transparent Solution to Hardware Piracy and Reverse EngineeringLeon Li, Alex Orailoglu. 1275-1281 [doi]
• Efficient and Secure Cloud-based Split Logic SynthesisChaitali Sathe, Yiorgos Makris, Benjamin Carrión Schäfer. 1282-1287 [doi]
• Efficient Key Switching Accelerator for Fully Homomorphic EncryptionSeoyoon Jang, Sungjin Park, Dongsuk Jeon. 1288-1294 [doi]
• The Unlikely Hero: Nonidealities in Analog Photonic Neural Networks as Built-in Adversarial DefendersHaotian Lu, Ziang Yin, Partho Bhoumik, Sanmitra Banerjee, Krishnendu Chakrabarty, Jiaqi Gu 0002. 1295-1301 [doi]
• Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted DataJianfei Wang 0003, Jia Hou, Fahong Zhang 0002, Yishuo Meng, Yang Su 0003, Chen Yang 0005. 1302-1307 [doi]
• PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot DetectionChen-Chia Chang, Wan-Hsuan Lin, Jingyu Pan, Guanglei Zhou, Zhiyao Xie, Jiang Hu, Yiran Chen 0001. 1308-1313 [doi]
• Efficient Hypergraph Modeling of VLSI Circuits for the MFS-Based Emulation and Simulation AccelerationJiahao Xu, Chunyan Pei, Shengbo Tong, Wenjian Yu. 1314-1320 [doi]
• ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate RestructuringMingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li 0001, Jing Ye 0001, Xiaowei Li 0001. 1321-1327 [doi]
• DEMOTIC: A Differentiable Sampler for Multi-Level Digital CircuitsArash Ardakani, Minwoo Kang, Kevin He, Qijing Huang 0001, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek. 1328-1335 [doi]
• Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA AccelerationZijian Jiang, Keran Zheng, David Boland, Yungang Bao, Kan Shi. 1336-1342 [doi]
• SISCO: Selective Invariant Sharing, Clustering and Ordering for Effective Multi-Property Formal VerificationSourav Das, Aritra Hazra, Pallab Dasgupta, Himanshu Jain, Sudipta Kundu. 1343-1349 [doi]
• CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect TransistorsShinobu Miwa, Eiichiro Sekikawa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda. 1350-1356 [doi]
• 3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric ControlYushen Zhang, Dragan Raseta, Tsun-Ming Tseng, Ulf Schlichtmann. 1357-1363 [doi]
• Dynamic Topology-Aware Flow Path Construction and Scheduling Optimization for Multilayered Continuous-Flow Microfluidic BiochipsMeng Lian 0001, Shucheng Yang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. 1364-1371 [doi]
• A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip TopologiesZhidan Zheng, You-Jen Chang, Liaoyuan Cheng, Tsun-Ming Tseng, Ulf Schlichtmann. 1372-1378 [doi]
• GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist RasterizationYiyang Sun, Peiran Yan, Yiqi Jing, Le Ye, Tianyu Jia. 1379-1385 [doi]
• Via Fabrication with Multi-Row Guiding Templates Using Lamellar DSAYun-Na Tsai, Shao-Yun Fang. 1386-1391 [doi]
• SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power OptimizationYikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma. 1392-1398 [doi]
• Robust Technology-Transferable Static IR Drop Prediction Based on Image-to-Image Machine LearningChao-Chi Lan, Chuan-Chi Su, Yuan-Hsiang Lu, Yao-Wen Chang. 1399-1405 [doi]
• T-Fusion: Thermal Modeling of 3D ICs with Multi-fidelity FusionBingrui Zhang, Wei Xing, Xin Zhao, Yuquan Sun. 1406-1412 [doi]
• Towards Functional Safety of Neural Network Hardware Accelerators: Concurrent Out-of-Distribution Detection in Hardware Using Power Side-Channel AnalysisVincent Meyers, Michael Hefenbrock, Mahboobe Sadeghipourrudsari, Dennis Gnad, Mehdi B. Tahoori. 1413-1419 [doi]
• Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic OperationDondee Navarro, Shin Taniguchi, Chika Tanaka, Kazutoshi Kobayashi, Takashi Sato 0001, Michihiro Shintani. 1420-1425 [doi]
• Cryo-Compact Modeling Based on Sparse Gaussian ProcessTetsuro Iwasaki, Takashi Sato 0001, Michihiro Shintani. 1426-1431 [doi]
• Re-Consideration of Correlation Between Interface States and Bulk Traps Using Cryogenic MeasurementYuichiro Mitani, Tatsuya Suzuki, Yohei Miyaki. 1432-1437 [doi]
• Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8KTakuma Kawakami, Takashi Sato 0001, Hiromitsu Awano. 1438-1443 [doi]
• Cryo-CMOS Analog Circuits for Spin Qubit ControlTakuji Miki. 1444-1449 [doi]