A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor - researchr publication

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Yuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge. A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. In Yuichi Nakamura 0002, Yu Wang 0002, editors, Proceedings of the 30th Asia and South Pacific Design Automation Conference, ASPDAC 2025, Tokyo, Japan, January 20-23, 2025. pages 325-327, ACM, 2025. [doi]

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