Kenichi Okada 0001 - researchr alias

m-boosting in 65 nm CMOS for millimeter-wave MIMO applicationsYi Zhang 0092, Minzhe Tang, Dongfan Xu, Jian Pang, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada 0001. ieiceee, 22(6):20250033, 2025. [doi]

A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data RateYi Zhang 0092, Minzhe Tang, Zheng Li 0021, Dongfan Xu, Kazuaki Kunihiro, Hiroyuki Sakai 0009, Atsushi Shirane, Kenichi Okada 0001. aspdac 2025: 342-343 [doi]

Experimental Testbed for Frequency-Division Multiplexed Joint Radar-Communication System Validation in D-Band Using a 65-nm CMOS Communication TransceiverCarrel da Gomez, Chenxin Liu, Hans Herdian, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Kenichi Okada 0001. access, 13:194063-194079, 2025. [doi]

A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error MeasurementYuibi Gomi, Akira Sato, Waleed Madany, Kenichi Okada 0001, Satoshi Adachi, Masatoshi Itoh, Masanori Hashimoto. lssc, 8:245-248, 2025. [doi]

NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency SynthesizersHongye Huang, Ashbir Aviat Fadila, Dingxin Xu, Waleed Madany, Wenqian Wang, Zezheng Liu, Yuang Xiong, Tianshi Hu, Bangan Liu, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada 0001. access, 13:146104-146115, 2025. [doi]

A 122 GHz Wirelessly Powered Active Reflector for D-Band CommunicationsMichihiro Ide, Keito Yuasa, Sena Kato, Shu Date, Takashi Tomura, Kenichi Okada 0001, Atsushi Shirane. lssc, 8:97-100, 2025. [doi]

Millimeter-Wave Wirelessly-Powered Phased-Array Relay Transceiver Utilizing CMOS Switching Rectifier-Type MixerSena Kato, Keito Yuasa, Michihiro Ide, Kenichi Okada 0001, Atsushi Shirane. ieicetc, 108(10):545-554, 2025. [doi]

11.1 A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite ConstellationsSena Kato, Jill C. Mayeda, Keito Yuasa, Michihiro Ide, Takeshi Ota, Shu Date, Yudai Yamazaki, Xiaolin Wang, Xi Fu, Dongwon You, Makoto Higaki, Jumpei Sudo, Hiroshi Takizawa, Masashi Shirakura, Takashi Tomura, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Kenichi Okada 0001, Atsushi Shirane. isscc 2025: 1-3 [doi]

Millimeter-wave GaAs Rectifier with Differential Signal 4:1 Power Combiner for Simultaneous Wireless Information and Power TransmissionMasayuki Kikuchi, Michihiro Ide, Jill C. Mayeda, Sena Kato, Keito Yuasa, Kenichi Okada 0001, Atsushi Shirane. lascas 2025: 1-5 [doi]

A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver ChipsetChenxin Liu, Zheng Li 0021, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Minzhe Tang, Dingxin Xu, Shinsuke Hara, Akifumi Kasamatsu, Takashi Tomura, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada 0001. jssc, 60(4):1132-1149, April 2025. [doi]

A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112-170 GHz for 6G TransceiversChenxin Liu, Yudai Yamazaki, Anyi Tian, Chun Wang, Hans Herdian, Abanob Shehata, Han Nie, Minzhe Tang, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada 0001. lssc, 8:241-244, 2025. [doi]

A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMOChenxin Liu, Zheng Li 0021, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Shinsuke Hara, Akifumi Kasamatsu, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada 0001. aspdac 2025: 354-355 [doi]

A 0.8-1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise CancellationWaleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Jill C. Mayeda, Atsushi Shirane, Kenichi Okada 0001. access, 13:40210-40225, 2025. [doi]

A Compact D-Band Phase Shifter With 0.1-Degree Phase Resolution and Ultra-Low Phase Error in 65-nm CMOSTakaya Uchino, Yudai Yamazaki, Anyi Tian, Chenxin Liu, SungHwan Park, Abanob Shehata, Sena Kato, Takumi Kojima, Haruto Tanaka, Masayuki Kikuchi, Jill C. Mayeda, Ryuji Kinugawa, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada 0001. jssc, 60(10):3566-3576, October 2025. [doi]

A LEO Satellite Mounted 256-Element 19 GHz CMOS Phased-Array Transmitter With On-Chip Amplitude and Phase MonitorXiaolin Wang, Dongwon You, Xi Fu, Gao Yuan, Takeshi Ota, Jill C. Mayeda, Jun Sakamaki, Ashbir Aviat Fadila, Makoto Higaki, Jumpei Sudo, Hiroshi Takizawa, Masashi Shirakura, Takashi Tomura, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Kenichi Okada 0001, Atsushi Shirane. access, 13:148893-148901, 2025. [doi]

A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz ReferenceDingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun 0001, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada 0001. jssc, 60(3):1043-1055, March 2025. [doi]

A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional SpurDingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun 0001, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang 0092, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada 0001. jssc, 60(6):2106-2121, June 2025. [doi]

A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NRDongfan Xu, Minzhe Tang, Yi Zhang 0092, Zheng Li 0021, Jian Pang, Atsushi Shirane, Kenichi Okada 0001. aspdac 2025: 352-353 [doi]

CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma ModulatorYuncheng Zhang, Zezheng Liu, Duo Li, Minzhe Tang, Yi Zhang 0092, Hongye Huang, Dingxin Xu, Waleed Madany, Ashbir Aviat Fadila, Wenqian Wang, Yuang Xiong, Daxu Zhang, Garry Pranata Kusuma, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada 0001. jssc, 60(12):4633-4646, December 2025. [doi]

A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated JitterDaxu Zhang, Dingxin Xu, Hongye Huang, Waleed Madany, Zezheng Liu, Wenqian Wang, Yuang Xiong, Ashbir Aviat Fadila, Duo Li, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada 0001. cicc 2025: 1-3 [doi]

5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAMYuncheng Zhang, Zezheng Liu, Duo Li, Minzhe Tang, Yi Zhang 0092, Hongye Huang, Dingxin Xu, Waleed Madany, Ashbir Aviat Fadila, Wenqian Wang, Yuang Xiong, Daxu Zhang, Garry Pranata Kusuma, Hiroyuki Sakai 0009, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada 0001. isscc 2025: 100-103 [doi]

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