Abstract is missing.
- Memory Aware Packet Matching Architecture for High-Speed NetworksMichal Kekely, Lukas Kekely, Jan Korenek. 1-8 [doi]
- Real-Time Emulation of Multiple NAND Flash Channels by Exploiting the DRAM Memory of High-end ServersNikolaos Toulgaridis, Eleni Bougioukou, Theodore Antonakopoulos. 9-15 [doi]
- High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGAInayat Ullah, Umar Afzaal, Zahid Ullah, Jeong-A Lee. 16-21 [doi]
- Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural NetworksShen-Fu Hsiao, Yu-Chang Chen, Hsiang-Hao Liang. 22-29 [doi]
- Measurement Based Execution Time Analysis of GPGPU Programs via SE+GAAdrian Horga, Sudipta Chattopadhyay 0001, Petru Eles, Zebo Peng. 30-37 [doi]
- Heavy-Hitter Detection Using a Hardware Sketch with the Countmin-CU AlgorithmAntonio Saavedra, Cecilia Hernández, Miguel Figueroa. 38-45 [doi]
- A Novel Hardware-Accelerated Priority Queue for Real-Time SystemsLukás Kohutka, Lukás Nagy, Viera Stopjaková. 46-53 [doi]
- Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign MagnitudeLuc Waeijen, Hailong Jiao, Henk Corporaal, Yifan He. 54-61 [doi]
- Trends in On-chip Dynamic Resource ManagementKasra Moazzemi, Anil Kanduri, David Juhasz, Antonio Miele, Amir M. Rahmani, Pasi Liljeberg, Axel Jantsch, Nikil D. Dutt. 62-69 [doi]
- FPGA Placement Improvement Using a Genetic Algorithm and the Routing Algorithm as a Cost FunctionFrancisco-Javier Veredas, Enrique J. Carmona. 70-76 [doi]
- Fault-Tolerant Deployment of Dataflow Applications Using Virtual ProcessorsReinier van Kampenhout, Sander Stuijk, Kees Goossens. 77-84 [doi]
- Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot DetectionGaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi. 85-90 [doi]
- Multimodal Image Registration between SWIR and LWIR Images in an Embedded SystemJavier Cardenas, Miguel Figueroa. 91-98 [doi]
- A Reconfigurable Fractional Interpolation Hardware for VVC Motion CompensationHasan Azgin, Ahmet Can Mert, Ercan Kalali, Ilker Hamzaoglu. 99-103 [doi]
- Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative DecodingOana Boncalo, Alexandru Amaricai, Sergiu Nimara. 104-109 [doi]
- High-Throughput One-Channel RS(255, 239) DecoderGabriele Perrone, Javier Valls, Vicente Torres, Francisco Miguel Garcia-Herrero. 110-114 [doi]
- COSSIM: An Open-Source Integrated Solution to Address the Simulator Gap for Systems of SystemsAndreas Brokalakis, Nikolaos Tampouratzis, Antonios Nikitakis, Ioannis Papaefstathiou, Stamatis Andrianakis, Danilo Pau, Emanuele Plebani, Marco Paracchini, Marco Marcon, Ioannis Sourdis, Prajith Ramakrishnan Geethakumari, Maria Carmen Palacios, Miguel Angel Anton, Attila Szasz. 115-120 [doi]
- Compositional Dataflow Modelling for Cyclo-Static ApplicationsHadi Alizadeh Ara, Marc Geilen, Amir R. B. Behrouzian, Twan Basten, Dip Goswami. 121-129 [doi]
- Timing Prediction for Service-Based Applications Mapped on Linux-Based Multi-core PlatformsRuben Jonk, Jeroen Voeten, Marc Geilen, Twan Basten, Ramon R. H. Schiffelers. 130-139 [doi]
- Modeling RISC-V Processor in IP-XACTEsko Pekkarinen, Timo D. Hämäläinen. 140-147 [doi]
- KETCube - The Universal Prototyping IoT PlatformJan Belohoubek, Jirí Cengery, Jaroslav Freisleben, Petr Kaspar, Ales Hamácek. 148-154 [doi]
- Flexible and Resource Efficient FPGA-Based Quad Data Rate Memory Interface Design for High-Speed Data Acquisition SystemsNizam Ayyildiz. 155-158 [doi]
- Design and Implementation of an HCI Based Peer to Peer APDU ProtocolLukas Gressl, Ulrich Neffe, Christian Steger. 159-162 [doi]
- Visualization of Memory Map Information in Embedded System DesignMikko Teuho, Esko Pekkarinen, Timo D. Hämäläinen. 163-166 [doi]
- A Versatile PCM-Based Circuits Emulator and Its Use on Implementing Linear Algebra FunctionsAnastasios Petropoulos, Theodore Antonakopoulos. 167-171 [doi]
- Embedded Operating System Optimization through Floating to Fixed Point Compiler TransformationDaniele Cattaneo, Antonio Di Bello, Stefano Cherubin, Federico Terraneo, Giovanni Agosta. 172-176 [doi]
- Attack Surface Modeling and Assessment for Penetration Testing of IoT System DesignsYasamin Mahmoodi, Sebastian Reiter 0003, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel. 177-181 [doi]
- DUSTER: DUal Source Write TERmination Method for STT-RAM MemoriesSaaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi. 182-189 [doi]
- Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTLTooba Arifeen, Abdus Sami Hassan, Jeong-A Lee. 190-195 [doi]
- Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication CheckingUmar Afzaal, Abdus Sami Hassan, Tooba Arifeen, Jeong-A Lee. 196-200 [doi]
- D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-FlopOliver Schrape, Anselm Breitenreiter, Marko S. Andjelkovic, Milos Krstic. 201-205 [doi]
- Optimal Dependability and Fine Granular Error Resilience Methodology for Reconfigurable SystemsFarnoosh Hosseinzadeh, Petr Pfeifer, Heinrich Theodor Vierhaus. 206-213 [doi]
- Program Generation Through a Probabilistic Constrained GrammarOndrej Cekan, Jakub Podivinsky, Zdenek Kotásek. 214-220 [doi]
- A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGAMahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Roel Jordans, Henk Corporaal. 221-228 [doi]
- Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot ControllerJakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek. 229-236 [doi]
- MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational CircuitsAmir M. Hajisadeghi, Hossein Bardareh, Hamid R. Zarandi. 237-243 [doi]
- FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design AutomationJakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek. 244-251 [doi]
- A Hypervisor Architecture for Low-Power Real-Time Embedded SystemsTomaso Poggi, Peio Onaindia, Mikel Azkarate-askasua, Kim Grüttner, Maher Fakih, Salvador Peiro Frasquet, Patricia Balbastre. 252-259 [doi]
- Segmentation of Hyperspectral Images Using Quantized Convolutional Neural NetworksPablo Ribalta Lorenzo, Michal Marcinkiewicz, Jakub Nalepa. 260-267 [doi]
- Design of a Low-Level Radar and Time-of-Flight Sensor Fusion FrameworkJosef Steinbaeck, Christian Steger, Gerald Holweg, Norbert Druml. 268-275 [doi]
- Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple LevelsShen-Fu Hsiao, Chen-Yen Tsai. 276-279 [doi]
- Intelligent Security Measures for Smart Cyber Physical SystemsMuhammad Shafique 0001, Faiq Khalid, Semeen Rehman. 280-287 [doi]
- Designing Energy Efficient Approximate Multipliers for Neural AccelerationSayandip De, Jos Huisken, Henk Corporaal. 288-295 [doi]
- Resource-Aware Decentralization of a UKF-Based Cooperative Localization for Networked Mobile RobotsSeyyed Ahmad Razavi, Eli Bozorgzadeh, Kanghee Kim, Solmaz Kia. 296-303 [doi]
- Design Optimization of Cyber-Physical Systems by Partitioning and Coordination: A Study on Mechatronic SystemsPouya Mahdavipour Vahdati. 304-311 [doi]
- Stability Verification of Self-Timed Control Systems Using Model-CheckingViktorio Semir el Hakim, Marco Jan Gerrit Bekooij. 312-319 [doi]
- Optimising Quality-of-Control for Data-Intensive Multiprocessor Image-Based Control Systems Considering Workload VariationsSajid Mohamed, Diqing Zhu, Dip Goswami, Twan Basten. 320-327 [doi]
- Circuit Inspired Modeling Method for IrrigationDavit Hovhannisyan, Ahmed M. Eltawil, Mohammad Abdullah Al Faruque, Fadi J. Kurdahi. 328-335 [doi]
- A Heuristic for Variable Re-Entrant Scheduling ProblemsRoel van der Tempel, Joost van Pinxten, Marc Geilen, Umar Waqas. 336-341 [doi]
- Building Distributed Co-Simulations Using CoHLAThomas Nägele, Jozef Hooman, Jack Sleuters. 342-346 [doi]
- RailCheck: A WSN-Based System for Condition Monitoring of Railway InfrastructureJan Sramota, Amund Skavhaug. 347-351 [doi]
- Co-simulation Framework for Control, Communication and Traffic for Vehicle PlatoonsAmr Ibrahim, Chetan Belagal Math, Dip Goswami, Twan Basten, Hong Li. 352-356 [doi]
- Quantization of Constrained Processor Data Paths Applied to Convolutional Neural NetworksBarry de Bruin, Zoran Zivkovic, Henk Corporaal. 357-364 [doi]
- CoNNA - Compressed CNN Hardware AcceleratorRastislav J. R. Struharik, Bogdan Vukobratovic, Andrea Erdeljan, Damjan Rakanovic. 365-372 [doi]
- Run-time Mapping Algorithm for Dynamic Workloads on Heterogeneous MPSoCs PlatformsSima Sinaei, Omid Fatemi. 373-380 [doi]
- FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network TrainingSajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese. 381-388 [doi]
- Generation of a Diagnosis Model for Hybrid-Electric Vehicles Using Machine LearningSimon Meckel, Roman Obermaisser, Jie-Uei Yang. 389-396 [doi]
- ADONN: Adaptive Design of Optimized Deep Neural Networks for Embedded SystemsMohammad Loni, Masoud Daneshtalab, Mikael Sjödin. 397-404 [doi]
- Embedded Real-Time Fall Detection with Deep Learning on Wearable DevicesEmanuele Torti, Alessandro Fontanella, Mirto Musci, Nicola Blago, Danilo Pau, Francesco Leporati, Marco Piastra. 405-412 [doi]
- A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract SpecificationsElena Zennaro, Lorenzo Servadei, Keerthikumara Devarajegowda, Wolfgang Ecker. 413-420 [doi]
- Inter-Patient ECG Classification Using Deep Convolutional Neural NetworksJanne Takalo-Mattila, Jussi Kiljander, Juha-Pekka Soininen. 421-425 [doi]
- Self-Aware Wearable Systems in Epileptic Seizure DetectionFarnaz Forooghifar, Amir Aminifar, David Atienza Alonso. 426-432 [doi]
- Exploring the Usage of Time-of-Flight Cameras for Contact and Remote PhotoplethysmographyCaterina Nahler, Bernhard Feldhofer, Matthias Ruether, Gerald Holweg, Norbert Druml. 433-441 [doi]
- SEEK: SIP-Based Emergency Embedded Framework Supports Elderly and Disabled to Perform Emergency CallsFoteini Andriopoulou, Anastasios Fanariotis, Theofanis Orphanoudakis. 442-449 [doi]
- Virtual White Cane Featuring Time-of-Flight 3D Imaging Supporting Visually Impaired UsersNorbert Druml, Thomas Pietsch, Markus Dielacher, Christian Steger, Marcus Baumgart, Cristina Consani, Thomas Herndl, Gerald Holweg. 450-457 [doi]
- The Accuracy and Efficacy of Real-Time Compressed ECG Signal Reconstruction on a Heterogeneous Multicore Edge-DeviceMohammed Al Disi, Hamza Djelouat, Abbes Amira, Faycal Bensaali. 458-463 [doi]
- MATISSE: A Smart Hospital EcosystemChristos Zachariadis, Terpsichori Helen Velivassaki, Theodore B. Zahariadis, Konstantinos Railis, Helen C. Leligou. 464-471 [doi]
- A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction PlatformDakila Serasinghe, Duvindu Piyasena, Ajith Pasqual. 472-478 [doi]
- Towards Spectral Pulse Oximetry Independent of Motion ArtifactsAlejandro Von Chong, Mehdi Terosiet, Aymeric Histace, Olivier Romain. 479-483 [doi]
- Toward an OFDM-Based Technique for Electrochemical Impedance SpectroscopyEdwin De Roux, Mehdi Terosiet, F. Kolbl, M. Boissiere, Aymeric Histace, Olivier Romain. 484-487 [doi]
- Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal ProcessingHelder H. Avelar, João Canas Ferreira. 488-491 [doi]
- Guards in Action: First-Order SCA Secure Implementations of Ketje Without Additional RandomnessVictor Arribas, Svetla Nikova, Vincent Rijmen. 492-499 [doi]
- OpenSSL Bellcore's Protection Helps Fault AttackSebastien Carre, Matthieu Desjardins, Adrien Facon, Sylvain Guilley. 500-507 [doi]
- Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI TechnologyJean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata. 508-515 [doi]
- An FPGA Hardware Trojan Detection Approach Based on Multiple Parameter AnalysisApostolos P. Fournaris, Lampros Pyrgas, Paris Kitsos. 516-522 [doi]
- Dummy Rounds as a DPA Countermeasure in HardwareStanislav Jerabek, Jan Schmidt, Martin Novotný, Vojtech Miskovský. 523-528 [doi]
- CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow IntegrityJean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, Abdelmalek Si-Merabet, Michaël Timbert. 529-536 [doi]
- Reliability Driven Mixed Critical Tasks Processing on FPGAs Against Hardware Trojan AttacksKrishnendu Guha, Atanu Majumder, Debasri Saha, Amlan Chakrabarti. 537-544 [doi]
- Design of a Fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic CurvesNiels Pirotte, Jo Vliegen, Lejla Batina, Nele Mentens. 545-552 [doi]
- An Improved Analysis of Reliability and Entropy for Delay PUFsAlexander Schaub 0001, Jean-Luc Danger, Sylvain Guilley, Olivier Rioul. 553-560 [doi]
- On the Importance of Analysing Microarchitecture for Accurate Software Fault ModelsJohan Laurent, Vincent Beroulle, Christophe Deleuze, Florian Pebay-Peyroula, Athanasios Papadimitriou. 561-564 [doi]
- Correlation Power Analysis Distinguisher Based on the Correlation Trace DerivativePetr Socha, Vojtech Miskovský, Hana Kubátová, Martin Novotný. 565-568 [doi]
- Feasibility of FPGA Accelerated IPsec on CloudMarkku Vajaranta, Vili Viitamaki, Arto Oinonen, Timo D. Hämäläinen, Ari Kulmala, Jouni Markunmaki. 569-572 [doi]
- Exploiting Phase Information in Thermal Scans for Stealthy Trojan DetectionMaxime Cozzi, Jean Marc Gallière, Philippe Maurine. 573-576 [doi]
- On the Design of a Processor Working Over Encrypted DataThomas Hiscock, Olivier Savry, Louis Goubin. 577-580 [doi]
- Low-Temperature Data Remanence Attacks Against Intrinsic SRAM PUFsNikolaos Athanasios Anagnostopoulos, Tolga Arul, Markus Rosenstihl, André Schaller, Sebastian Gabmeyer, Stefan Katzenbeisser 0001. 581-585 [doi]
- Design and Implementation of a Privacy Framework for the Internet of Things (IoT)Paris Panagiotou, Nicolas Sklavos, Ioannis D. Zaharakis. 586-591 [doi]
- The AQUAS ECSEL ProjectLuigi Pomante, Bohuslav Krena, Tomás Vojnar, Filip Veljkovic, Pacome Magnin. 592-599 [doi]
- ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance ComputingCristina Silvano, Giovanni Agosta, Andrea Bartolini, Andrea R. Beccari, Luca Benini, Loïc Besnard, João Bispo, Radim Cmar, João M. P. Cardoso, Carlo Cavazzoni, Stefano Cherubin, Davide Gadioli, Martin Golasowski, Imane Lasri, Jan Martinovic, Gianluca Palermo, Pedro Pinto, Erven Rohou, Nico Sanna, Katerina Slaninová, Emanuele Vitali. 600-607 [doi]
- A Review of Near-Memory Computing Architectures: Opportunities and ChallengesGagandeep Singh, Lorenzo Chelini, Stefano Corda, Ahsan Javed Awan, Sander Stuijk, Roel Jordans, Henk Corporaal, Albert-Jan Boonstra. 608-617 [doi]
- PRYSTINE - PRogrammable sYSTems for INtelligence in AutomobilEsNorbert Druml, Georg Macher, Michael Stolz, Eric Armengaud, Daniel Watzenig, Christian Steger, Thomas Herndl, Andreas Eckel, Anna Ryabokon, Alfred Hoess, Sumeet Kumar, George Dimitrakopoulos, Herbert Roedig. 618-626 [doi]
- Resource Management for Mixed-Criticality Systems on Multi-core Platforms with Focus on CommunicationRobin Arbaud, David Juhasz, Axel Jantsch. 627-641 [doi]
- Exploration of the Synchronization Constraint in Quantum-dot Cellular AutomataFrank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler. 642-648 [doi]
- Evaluating the Impact of Interconnections in Quantum-Dot Cellular AutomataFrank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler. 649-656 [doi]
- From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETsJan Nevoral, Richard Ruzicka, Vaclav Simek. 657-664 [doi]
- Towards Reversed Approximate Hardware DesignSaman Fröhlich, Daniel Große, Rolf Drechsler. 665-671 [doi]
- On Designing All-Optical Multipliers Using Mach-Zender InterferometersSumit Sharma 0002, Krishnendu Chakrabarty, Sudip Roy 0001. 672-679 [doi]
- Optimization of Circuits for IBM's Five-Qubit Quantum ComputersGerhard W. Dueck, Anirban Pathak, Md. Mazder Rahman, Abhishek Shukla, Anindita Banerjee. 680-684 [doi]
- Classifying Acoustic Signals for Wildlife Monitoring and Poacher Detection on UAVsCarlo Lopez-Tello, V. Muthukumar. 685-690 [doi]
- A Markovian Decision Process Analysis of Experienced Agents Joining Ad-Hoc TeamsRoghaiyeh Heidari, Mohsen Afsharchi, Reza Khanmohammadi. 691-698 [doi]
- Identity and Access Management with Blockchain in Electronic Healthcare RecordsTomas Mikula, Rune Hylsberg Jacobsen. 699-706 [doi]
- Development of Autonomous Drones for Adaptive Obstacle Avoidance in Real World EnvironmentsArne Devos, Emad Ebeid, Poramate Manoonpong. 707-710 [doi]
- Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs Using GALIRazi Seyyedi, Sören Schreiner, Maher Fakih, Kim Grüttner, Wolfgang Nebel. 711-718 [doi]
- Exploring Power and Throughput for Dataflow Applications on Predictable NoC MultiprocessorsKathrin Rosvall, Tage Mohammadat, George Ungureanu, Johnny Öberg, Ingo Sander. 719-726 [doi]
- A Reliable Statistical Analysis of the Best-Fit Distribution for High Execution TimesXavier Civit, Joan del Castillo, Jaume Abella. 727-734 [doi]
- Virtual Switch Supporting Time-Space Partitioning and Dynamic Configuration for Integrated Train Control and Management SystemsHongjie Fang, Roman Obermaisser. 735-739 [doi]
- Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW PartitionsVittoriano Muttillo, Giacomo Valente, Luigi Pomante. 740-744 [doi]