Shin'ichi Wakabayashi - researchr alias

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Viewing Publication 1 - 25 from 25

2023

Feature Vectors Based on Wire Width and Distance for Lithography Hotspot DetectionGaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi. ipsj, 16:2-11, 2023. [doi]

2022

Introduction of a New Method for Preventing Recipient Unapproved Transactions to Bitcoin WalletChuki Hayama, Yoko Kamidoi, Shin'ichi Wakabayashi. compsac 2022: 767-772 [doi]

2021

A Protocol for Preventing Transaction Commitment Without Recipient's Authorization on Blockchain and It's ImplementationYoko Kamidoi, Ryousuke Yamauchi, Shin'ichi Wakabayashi. access, 9:24390-24405, 2021. [doi]

2020

A Framework for Fast MapReduce Processing Considering Sensitive Data on Hybrid CloudsShun Kawamoto, Yoko Kamidoi, Shin'ichi Wakabayashi. compsac 2020: 1357-1362 [doi]

A Verifiable Secret Sharing Scheme without Using Multi-Party ComputationsTakumi Makino, Yoko Kamidoi, Shin'ichi Wakabayashi. compsac 2020: 845-850 [doi]

2018

2016

An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming dataYuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi. fpt 2016: 257-260 [doi]

2015

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various TopologiesMasato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi. ieicet, 98-A(12):2572-2583, 2015. [doi]

2014

An ILP-Based Optimal Circuit Mapping Method for PLDsHiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko. ipps 2014: 251-256 [doi]

An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern UpdatingYoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi. ipsj, 7:110-118, 2014. [doi]

2013

A Multithreaded Parallel Global Routing Method with Overlapped Routing RegionsYasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi. dsd 2013: 591-597 [doi]

A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGAYoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi. dsd 2013: 293-296 [doi]

2011

A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear InterpolationsSatoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi. dsd 2011: 701-707 [doi]

An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene OperatorsYoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama. fpl 2011: 157-161 [doi]

2008

A systolic regular expression pattern matching engine and its application to network intrusion detectionYosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama. fpt 2008: 297-300 [doi]

2007

A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA ImplementationYoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama. fpt 2007: 261-264 [doi]

2006

FPGA implementation of tabu search for the quadratic assignment problemShin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama. fpt 2006: 269-272 [doi]

2002

A Performance-Driven Floorplanning Method with Interconnect Performance EstimationShinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide. ieiceta, 85-A(12):2775-2784, 2002. [doi]

1997

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIsTetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru. aspdac 1997: 133-140 [doi]

1993

A new global routing algorithm for over-the-cell routing in standard cell layoutsTetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida. eurodac 1993: 116-121 [doi]

1992

An optimal channel pin assignment with multiple intervals for building block layoutTetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida. eurodac 1992: 348-353 [doi]

1989

Visualized and modeless programming environment for form manipulation languageJun'ichi Miyao, Shin'ichi Wakabayashi, Noriyoshi Yoshida, Yasushi Ohtahara. vl 1989: 99-104 [doi]

1985

Design of hardware algorithms by recurrence relationsShin'ichi Wakabayashi, Tohru Kikuno, Noriyoshi Yoshida. scjapan, 16(3):10-18, 1985. [doi]

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